App note: Implementing a TMDS video interface in the Spartan-6 FPGA


Implementing a TMDS video interface in the Spartan-6 FPGA, an app note here (PDF!) from Xilinx:

The DVI and HDMI protocols use TMDS at the physical layer. The TMDS throughput is a function of the serial data rate of the video screen mode being transmitted. This in turn determines the FPGA speed grade that must be used to support this throughput. After the Spartan-3A family, Xilinx has offered embedded electrically-compliant TMDS I/O allowing implementation of DVI and HDMI interfaces inside the FPGA. The operation theory for this is detailed in Video Connectivity Using TMDS I/O in Spartan-3A FPGAs. The data throughput in that application note was maximized at 666 Mb/s in the fastest speed grade. The Spartan-6 FPGA on the other hand has made significant speed improvements. Table 1 shows the maximum throughput for each speed grade of the Spartan-6 FPGA.

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