App note: High-speed input clock issues

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Clock jitter are a big issue in high-speed ADC, here’s an application note from e2V to guide users deals with these problems. Link here (PDF)

The e2v converters family addresses the high-speed market in the field of ADCs as well as DACs, with frequencies operating in the GHz range. Such high-speed devices require high-speed clock signals, which are usually subject to noise and wich users are not used to deal with. As a matter of fact, the clock signal integrity is one of the main factor to be taken into account for proper operation of an ADC.

High-speed ADCs require a low phase noise clock (namely a low jitter clock) in order to limit the dynamic performance degration caused by noise on the clock. Event though many manufacturers offer crystal oscillators with the right jitter characteristics, only a few are able to generate clocks in the GHz range.

These two issues are addressed in this paper, which intends to help the user understand the jitter phenomenon and design a proper clock with the right performance.

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