Bus Pirate “Ultra” HDL moves from simulation to real hardware

Latest simulation of Bus Pirate Ultra HDL

The HDL is complete enough to start testing on real hardware. This update puts almost every feature under control of the state machine in the FPGA so commands can be pipelined with repeatable precision. Commands (write/read SPI, set/clear pin, measure voltage, update PWM, enable pull-up resistors, etc) are pushed into a FIFO buffer using a 17bit command/data protocol inspired by the interface of ST7789-based LCDs. When the state machine is enabled the commands are processed in one continuous stream.

Verilog HDL for the FPGA is on github, the latest updates are currently on the command-data-refactor branch. A synthesized version of the bitstream is in the forum.

giggiu16 has already build a v1d. There are a few more boards to give away, if you’d like one please message Ian in the forum.

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