is complete enough to start testing on real hardware. This update puts
almost every feature under control of the state machine in the FPGA so
commands can be pipelined with repeatable precision. Commands
(write/read SPI, set/clear pin, measure voltage, update PWM, enable
pull-up resistors, etc) are pushed into a FIFO buffer using a 17bit
command/data protocol inspired by the interface of ST7789-based LCDs.
When the state machine is enabled the commands are processed in one
We’ve been prototyping the Bus Pirate Ultra with a 240 x 320 pixel 2 inch LCD, but it’s just a bit small and hard to read from a distance. A 2.8 inch version is available that fits the full width of the Bus Pirate PCB, with the trade off of bigger pixels/lower pixel density. We bought a few displays from various “manufacturers” on Taobao and made up a daughterboard. It failed spectacularly because the datasheet was so wrong!
We don’t have to go beyond pin 1 to find a major and obvious error. The datasheet lists pin 1 as the LED backlight anode, and pins 2-5 as the cathode. The printing on the flex connector makes it clear that four cathodes (K1-4) join into a single trace to pin 1. A single anode (A) trace connects to four pads on the connector (pins 2-5). The backlight connections are backwards.
Coincidentally, datasheets for other similar displays (2.8 inch, 50 pin connector) match the corrected pinout. This datasheet just had it backwards. We reversed the backlight power and ground on the PCB by drilling out a trace and creating some strategic solder bridges. While the LEDs light, the display doesn’t respond to any commands so other connections could be wrong.
That’s not all. The flex cable is actually several millimeters shorter than listed in the datasheet, so it can’t reach the connector through the slot in the daughterboard.
We had similar issues with this supplier’s 2 inch display. The dimensions in the datasheet are a bit off, and their sample initialization code doesn’t work. We asked for an updated datasheet and received three different versions, none of which matched the actual display.
Their Taobao page has pictures of a factory and a nice section on after sales support. A charitable guess is that they manufacture runs of custom displays, and sell the excess on Taobao. That would explain all the different datasheets they so readily have available. We tried to get another grab-bag of PDFs for the 2.8 inch display, one of which might match the actual pinout, but at this point they got tired and ghosted us.
Will we stop buying prototyping samples on Taobao and 1688? Definitely not! It’s a great way to see what’s a cheap commodity product. This process plays out in the Shenzhen markets as well, people sell a lot of stuff without knowing exactly what it is. It’s kind of up to us to know what we’re buying, and sometimes it’s a crapshoot. When we find a sample we like, it’s time to send someone up to the factory to meet the boss, drink way too much tea, and ensure we’ll have a steady and consistent supply in the future.
Bus Pirate “Ultra” v1d is stuffed and about half tested. This should be the last alpha “figuring out if we can pull this off” version. New in this revision:
Analog voltage measurement is now done from the FPGA using a 12bit 1 million samples per second ADS7042 Analog to Digital Converter. This will let us pipeline voltage measurement commands with other bus commands and reduce dependency on any specific MCU.
The programmable output power supply is now controlled by a DAC104S085CIMM Digital to Analog Converter chip, instead of the DAC in the MCU. This further reduces our dependency on a specific MCU, and will later allow us to control the voltage regulator from the command pipeline in the FPGA. It may be possible to simulate different power supply conditions and glitches, for example.
A lot more thought
went into the programmable output power supply. V1d measures current
through a shunt resistor, and we added a small load to test it.
There’s several other goodies in there, but we’ll reveal them later.
In addition to sampling voltages on each IO pin from the FPGA, we’re now sampling several other voltages from around the board (power supply output, current consumption, etc) . We swapped the 8 channel 74HCT4051 analog multiplexer with a 74HCT4067 16 channel multiplexer. This part of the board needs some more thought because some of the voltages would be better measured without the divide by 2 resistor divider currently used after the op-amp.
The display daughter board now uses a 0.5mm pitch flex connector. We though these connectors and the flex cables would be a nightmare to work with, but they’re actually a lot of fun. They’re really compact too.
After a little more testing we’ll get to work on v1e, which should be the first beta and possibly the first version ready for a small production run. Find the latest updates and follow a group build of v1d in the forum.
The primary reason we ordered these now is to get a feel for how the pinout color scheme works in practice before we commit to it permanently.
The leads are 30cm long, which seems a bit unwieldy in real life. The next version will be a few centimeters shorter.
One end is terminated with 1 pin female “DuPont” connectors. These are easy to use with breakout boards and bread boards that have 2.54mm header pins. We’ll need to choose a nice probe hook and mating crimp eventually.
While the wire quality is fine (top), it’s a bit stiff and we’d prefer something really nice for the final cable. The Saleae Logic cable (bottom) has really amazing tangle free wire with great flexibility. We took the Saleae cable to a bunch of wire manufacturers in Shenzhen, but none of them had anything close in terms of quality and flexibility. Our search will continue.
In addition to the 2 inch IPS LCD we’re been using with the Bus Pirate prototype “Ultra”, we’re also sending off a PCB for a larger 2.8 inch display. Both panels are 240*320 pixels, so the larger version probably won’t look quite as stunning as the smaller display with high pixel density. If it does pass muster, a capacitive touch screen controller option is available that might be an interesting addition.
A differential pin pair can be used as a comparator to create a basic ADC. This app note shows how to design a low speed (1 KHz) and “high” speed (50 Khz) ADC technique using only FPGA pins, a resistor and a capacitor. Regardless of whether we ever use this technique, it is illuminating to understand how SAR and Delta Sigma ADCs are constructed:
A simple Analog to Digital Converter can be constructed by adding a small RC circuit to an LVDS input on an FPGA or CPLD…. The LVDS input will act as a simple analog comparator and will output a digital ‘1’ if the Analog Input voltage is higher than the voltage from the RC network. By changing the voltage on the input to the RC circuit, the LVDS comparator can be used to analyze the Analog Input voltage to create an accurate digital representation… A low frequency signal can be processed using a simple Successive Approximation Register… A higher frequency implementation…can be implemented using a Delta Sigma Modulator function, which consists of a sampling register and a Cascade Integrated Comb (CIC) Filter.