Flapjack TM Programmable IO Board
Flapjack TM – Fully programmable ISA bus I/O Board, using only through-hole parts. The Flapjack design is based on the Lattice ispLSI1032E-70LJ CPLD, in a socketed 84-pin PLCC package. There is only one integrated circuit on the board. This design is the minimum complexity design, because of the limited number of pins available in the socketable PLCC package. In order to minimize costs, this board is built on a two-sided board (i.e. no power or ground plane layers) with 10 mil lines and spaces.
Contents | File type | File name |
---|---|---|
Specification | Adobe Acrobat version 3 | flapjack.pdf 04-28-00, 196k |
Specification | html | flapspec.htm |
Schematics | zip of HPGL plotter files | flaphgl.zip 04-28-00, 167k |
CAD source files | zip of Tango Schematic 1.50, Tango PCB Plus 2.30 files | flaptan.zip 03-28-00, 45k |
CAD source files | zip of OrCad – PCB only | flaporc.zip |
CPLD source files | zip of VHDL, pin, configuration files | flapvhdl.zip 04-15-00, 10k |
CPLD programming files | zip of JEDEC file | flappgm.zip 04-15-00, 9k |
Manufacturing | zip of Gerber/Excellon/text | flapjack.zip 03-28-00, 136k |
GNU/Linux Drivers | user space driver (c code) | cb_user.tgz |
Wxx 16-bit Drivers | Zips of C code | testw16.zip – test programbasic_io.zip – basic IO example |
Hardware designer: Diehl Martin
Note: The source code for all designs shown here is released under the GNU General Public License.