Tag Archives: app note

App note: Clearing Xilinx FPGA configuration to allow boundary scan testing

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Another application note from XJTAG on preparing Xilinx FPGA for proper boundary scan testing. Link here

When Xilinx FPGAs are configured it can restrict the boundary scan access to some signals on the device. One work-around for this problem is to configure the FPGA with a ‘blank’ image that closely matches its unconfigured state, allowing boundary scan testing to occur without any problems.

A second issue that can affect boundary scan testing with FPGAs is that they contain pull resistors. Depending on the design, these may be enabled when the FPGA is unconfigured as well as when it is configured. If these internal resistors are enabled on nets that contain pull resistors mounted on the board, two potential problems can occur:

1. If the internal resistor and external resistor pull in opposite directions, the boundary scan tests may not be able to test the external pull resistor if it is weaker than the internal pull resistor.
2. If the internal and external resistors pull in the same direction, a fault with the external resistor may not be detected because the internal resistor may mask the fault.

By setting the correct configuration options it is possible to disable these internal pull resistors when generating a ‘blank’ FPGA image.

App note: Using a test reset section to initialise JTAG devices

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An app note from XJTAG about applying test reset to put some devices to JTAG compliant mode. Link here

Some JTAG devices require a specific sequence of states to be applied to some signals in order to put the device into a JTAG-compliant mode. This application note describes how a Test Reset section can be used to describe the required sequence and control its application.

App note: Linear power MOSFETS basic and applications

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Some examples of power MOSFETS application from this app note from IXYS Corporation. Link here (PDF)

Applications like electronic loads, linear regulators or Class A amplifiers operate in the linear region of the Power MOSFET, which requires high power dissipation capability and extended Forward Bias Safe Operating Area (FBSOA) characteristics. Such mode of operation differs from the usual way of using Power MOSFET, in which it functions like an “on-off switch” in switched-mode applications. In linear mode, the Power MOSFET is subjected to high thermal stress due to the simultaneous occurrence of high drain voltage and current resulting in high power dissipation. When the thermo-electrical stress exceeds some critical limit, thermal hot spots occur in the silicon causing the device to fail

App note: Depletion-Mode power MOSFETs and applications

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IXYS Corporation’s N-Channel power MOSFET selection and application. Link here (PDF)

Applications like constant current sources, solid-state relays, telecom switches and high voltage DC lines in power systems require N-channel Depletion-mode power MOSFET that operates as a normally “on” switch when the gate-to-source voltage is zero (VGS=0V). This paper will describe IXYS latest N-Channel Depletion power MOSFETs and their application advantages to help designers to select these devices in many industrial applications.