Tag Archives: app notes

App note: How to select the right thyristor (SCR) for your application

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SCR fundamentals discussed in this app note from STMicroelectronics. Link here (PDF)

This document provides some guidelines about how to select the right thyristor, also referred to as “SCR”, according to the different applications. Some very specific cases could require a higher level of expertise to ensure reliable and efficient operation.

 

App note: How to maintain USB signal integrity when adding ESD protection

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Introducing the eye diagram method in this app note from ON Semiconductors in determining signal integrity of USB lines. Link here (PDF)

The Universal Serial Bus (USB) has become a popular feature of PCs, cell phones and other electronic devices. USB makes data transfer between electronic devices faster and easier. USB 2.0 transfers data at up to 480 Mbps. At these data rates, any small amount of capacitance added will cause disturbances to the data signals. Designers are left with the challenge of finding ESD protection solutions that can protect these sensitive lines without adding signal degrading capacitance. This document will discuss USB 2.0 and evaluate the importance of low capacitance ESD protection devices with the use of eye diagrams.

App note: Low-side self-protected MOSFET

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Integrated fault protected MOSFET app note from ON Semiconductors. Link here (PDF)

The ever increasing density and complexity of automotive and industrial control electronics requires integration of components, wherever possible, so as to conserve space, reduce cost, and improve reliability. Integration of protection features with power switches continues to drive new product development. The often open environments of automotive and industrial electronics, subject to severe voltage transients, high power and high inductance loads, numerous external connections, and human intervention force the requirement of fault protection circuitry. Advancements in power MOSFET processing technology afford an economical marriage of protection features, such as current limitation, and standard MOSFET power transistor switches. This paper describes the technology and operation of ON Semiconductor’s HDPlus monolithic low-side smart MOSFET family.

App note: Capacitive sensing: Direct vs remote liquid-level sensing performance analysis

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Capacitive liquid level sensing method comparison discussed in this app note from Texas Instruments. Link here (PDF)

Capacitive-based liquid level sensing is making its way into the consumer, industrial, and automotive markets due to its system sensitivity, flexibility, and low cost. With using TI’s capacitive sensing technology, the system flexibility allows designers to have the choice of placing the sensors directly on the container (direct sensing) or in close proximity to the container (remote sensing). Each configuration has its own advantages and disadvantages. This application note highlights the system differences and performance of direct and remote sensing to provide guidance in how capacitive-based liquid-level sensing is affected.

App note: Measuring liquid levels using hall effect sensors

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App note from Infineon on methods used in liquid level measurement and how contactless hall effect sensors are the right choice for the job. Link here (PDF)

This application note is dedicated to liquid level sensing using non-contacting magnetic sensor technology. First, an overview of some liquid level sensor application requirements are given. Next, we will introduce some of the solutions that are employed today and are researched for future systems, including both contacting techniques as well as non-contacting methods. Magnetic sensing turns out to be a comparably easy and robust solution to tackle the problem and Infineon’s linear Hall sensor portfolio is presented. Different design aspects of a magnetic liquid level sensor, including magnetic circuit designs, are discussed. The last section introduces some of Infineon’s Hall effect sensors that are suitable for use in fuel level sensing.

App note: Trends in integrated circuits that affect ESD protection requirements

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A quick lookup on the ESD protection evolution of ICs in this app note from ON Semiconductor. Link here (PDF)

The stunning progress in integrated circuit capability over the last 40 years is most succinctly expressed by Moore’s Law; “Every 2 years the number of transistors that can be economically manufactured in an integrated circuit will double”. The secret to this success has been the shrinking of integrated circuit feature sizes in all three dimensions. To maintain circuit reliability with the smaller dimensions the operating voltage of integrated circuits has been steadily declining. This trend will continue in the future, as documented in the International Technology Roadmap for Semiconductors. As the working voltage for integrated circuits decreases the voltage at which circuit damage can occur also decreases.

The move to smaller geometries has also prompted fundamental changes in IC technologies that have had an adverse effect on the intrinsic ability of the technologies to survive ESD stress. A prime example is the evolution of nMOS transistors in CMOS technologies.