The primary reason we ordered these now is to get a feel for how the pinout color scheme works in practice before we commit to it permanently.
The leads are 30cm long, which seems a bit unwieldy in real life. The next version will be a few centimeters shorter.
One end is terminated with 1 pin female “DuPont” connectors. These are easy to use with breakout boards and bread boards that have 2.54mm header pins. We’ll need to choose a nice probe hook and mating crimp eventually.
While the wire quality is fine (top), it’s a bit stiff and we’d prefer something really nice for the final cable. The Saleae Logic cable (bottom) has really amazing tangle free wire with great flexibility. We took the Saleae cable to a bunch of wire manufacturers in Shenzhen, but none of them had anything close in terms of quality and flexibility. Our search will continue.
In addition to the 2 inch IPS LCD we’re been using with the Bus Pirate prototype “Ultra”, we’re also sending off a PCB for a larger 2.8 inch display. Both panels are 240*320 pixels, so the larger version probably won’t look quite as stunning as the smaller display with high pixel density. If it does pass muster, a capacitive touch screen controller option is available that might be an interesting addition.
Uses 10 pin 0.5mm flexible PCB connector, wired to the main board with a 1:N connection. This connector is much smaller and thinner than the 1.25mm connector on v1b, it reduces the space needed between the display board and the main board.
Flipped LCD orientation 180 degrees so font data can be written into bounding boxes in a more natural “left-to-right” orientation, eliminating the need to precalculate the text end point and write characters in reverse sequence
Nudged the display towards the IO header. We’ll experiment with some buttons in the remaining available space
Decoupling capacitors on LCD power pins
The 2 inch 240*320 IPS LCD display we’re been testing has a very pleasing pixel density, but we’re also itching to try the bigger 2.8 inch version. Next week we’ll send out a prototype carrier board for the bigger display, as well as some Bus Plug breakout boards.
Bus Pirate prototype Ultra v1b uses an FPGA to process commands sent through a FIFO buffer to a state machine. Pipelined commands can be loaded into the FIFO and executed by the state machine with per-clock repeatability. Non-pipelined commands halt the state machine while the MCU takes over to perform the command, the delay is unpredictable and depends on many factors such as USB operations the MCU may be servicing.
These commands are currently pipelined and handled in the FPGA by the state machine:
Delays (ms, us)
These commands can be pipelined, but are currently handled in registers:
These commands will be pipelined in v1c and later:
ADC reads (on any pin, Vout)
These commands could be pipelined with some hardware updates:
Pull-up resistors toggle
Power supply enable
Power supply margining (by adding an external DAC)
These commands cannot be pipelined because they happen outside the FPGA:
Mode change (reloads the FPGA)
Jump to bootloader
Self-test (involves tests on the MCU and FPGA)
There are also mode macros to consider, which probably need to be a combination of pipelined commands and non-pipelined commands. This week we’ll choose an external DAC and add it to the board.
Bus Pirate prototype “Ultra” v1b successfully wrote to and read back from a 25LC020A SPI EEPROM chip. The image shows the Bus Pirate reading 8 bytes of 0x02 from the EEPROM at address 0x00, and the bus activity can be verified on the logic analyzer graph. Still a long way to go, but it’s nice to have everything working.
Tomorrow we’ll finish the major SPI commands and general purpose mode features like analog measurement and manipulation of the auxiliary pins. As always, you can follow our latest progress in the forum.
Bus Pirate prototype “Ultra” version 1c is technically done, but we came up with some hot last minute additions this weekend. We’ll skip this board and send out the updated version 1d with the additional features at the end of the week.
Version 1c changes:
4 layer PCB
1MHz 12 bit SPI ADC connected directly to the FPGA
Vout/Vref is also measured through the analog multiplexer, which is changed to to the bigger 16bit version (74HCT4067). This will probably change to two 74HCT4051s instead because supplies of the 4067 are skimpy! We can have one “divide by two” 4051 for 5volt measurements on the IO pins, and one 3.3volt 4051 tied directly to the ADC for measuring lower voltage analog stuff
Beefier 3.3volt supply
The 1.2volt supply is now monitored by the MCU for self testing
0.5mm flex cable connector for the display board opens up a bit of board space
Additional ADC measurement point before the back-current shut down protection on the power supply. This gives us a way to include it in the self test and detect when it activates