Tag Archives: Embecosm

Embedded (Erlang, Parallella, Compiler Options and Energy Consumption)

via OSHUG

Embedded systems continue to grow in importance as they play an ever-increasing role in everyday life: more computing is done on the move as smartphone functionality catches up with desktops and services move to the Cloud; the Internet of Things is set to herald an age in which networked objects create and consume data on our behalves. These, and many other applications, are driving an insatiable demand for more powerful and energy-efficient embedded solutions.

At the twenty-second OSHUG meeting we will hear how Erlang can be used to bring concurrency to multi-core embedded systems, we will learn about the Parallella project which aims to make parallel computing accessible to everyone, and we will hear about vital research into optimising compiler options for energy-efficiency.

Erlang Embedded — Concurrent Blinkenlights and More!

Managing the resources and utilising the increasingly popular multi-core and heterogeneous aspects of modern embedded systems require new sets of tools and methodologies that differ from the traditional C/C++ flow.

Erlang provides features that are highly relevant to solve these issues and yet it is pretty much unknown in the embedded domain — which is surprising considering that it was originally designed for embedded applications at Ericsson!

This talk aims to provide an overview of Erlang and the current state of its usage in the embedded domain and talk about our plans to help speed up the adoption rate of Erlang in embedded projects.

Omer Kilic works on Erlang Embedded, a Knowledge Transfer Partnership project in collaboration with University of Kent. The aim of this project is to bring the benefits of concurrent systems development using Erlang to the field of embedded systems; through investigation, analysis, software development and evaluation.

Prior to joining Erlang Solutions, Omer was a research student in the Embedded Systems Lab at the University of Kent, working on a reconfigurable heterogeneous computing framework as part of his PhD thesis (which he intends to submit soon!)

Omer likes tiny computers, things that 'just work' and real beer.

Parallella — Supercomputing for Everyone

The Parallella computing platform is based on the Adapteva Epiphany processor. Implemented in 65nm or 28nm silicon, Epiphany offers 16 or 64 cores and delivers up to 50 GFLOPS/watt, and the entire Parallella board complete with a dual-core ARM A9 host will consume around 5 watts.

This talk will present the Epiphany architecture and explore the challenges of developing an effective GNU tool chain, and discuss the use of open source, and an approach to engineering that developed one of the fastest chips in the world from concept to second generation silicon for just a few million dollars.

Dr Jeremy Bennett is the founder of Embecosm, and an expert on hardware modelling and embedded software development. Prior to founding Embecosm, Dr Bennett was Vice President of ARC International PLC and previously Vice President of Marconi PLC.

In his earlier academic career, he pursued academic research in computer architecture, modelling and compiler technology at Bath and Cambridge Universities. He is the author of the popular textbook "Introduction to Compiling Techniques" (McGraw-Hill 1990, 1995, 2003).

Dr Bennett holds an MA and PhD in Computer Science from Cambridge University. He is a Member of the British Computer Society, a Chartered Engineer, a Chartered Information Technology Professional and Fellow of the Royal Society of Arts.

Measuring the impact of compiler options on energy consumption in embedded platforms

Energy efficiency is the highest priority for modern software-hardware co-design. The potential for compiler options to impact on power consumption of running programs has often been discussed. However there has never been a comprehensive analysis of the magnitude of that impact, or how it varies between processor architectures and compilers.

This presentation will describe a project undertook during the the Summer of 2012 at the University of Bristol Department of Computer Science and funded by Embecosm, to explore the effect of compiler options on energy consumption of compiled programs.

The talk will discuss the accurate measurement of power consumption on a range of small embedded systems. The whole setup was under control of an XMOS board, making it possible to run the tens of thousands of tests needed for statistical robustness in just a few weeks. The results of these tests will be discussed, the implications for compiling embedded systems, and the potential for future research in this area.

This research was unusual, in that it was funded as a completely open project. A wiki detailed progress from week to week, the relevant open source communities were kept regularly informed, and the results will be published in open access journals. The talk will also cover the issues around funding and running an academic research project in this manner.

James Pallister is a graduate of the University of Bristol, where he achieved joint First Class Honours in Computer Science and Electronics. During the summer of 2012, he led Embecosm's research program into the impact of compilers on energy consumption in embedded systems, which was a development of James' work at the University of Bristol with the XMOS multi-core processor.

Mr Pallister has returned to Bristol in October 2012, where he is studying for a PhD in low-power multi-core system design. He remains a Technical Advisor to Embecosm.

Simon Hollis is a lecturer in the Microelectronics Research Group, Department of Computer Science, University of Bristol. His interests lie in the creation of energy-efficient embedded systems, processor interconnects and parallel languages and run-times.

He is the creator of the RasP and Skip-link Networks-on-Chip, and is currently working on the Swallow many-core system, which targets 480 processing cores in under 200W. A main aim of the research is to re-investigate the memory/communication balance in large scale computing systems.

Note: Please aim to arrive for 18:45 or shortly after as the event will start at 19:00 prompt.

Practical System-on-Chip (Program your own open source FPGA SoC)

via OSHUG

At the ninth OSHUG meeting we were given an introduction to FPGA development, and to the OpenCores community and the OpenRISC 1000 open source processor family. At the seventeenth OSHUG meeting we will be given a comprehensive introduction to the practicalities of programming your own open source FPGA system-on-chip.

How to Program Your Own Open Source FPGA System-on-Chip

It is possible to buy a FPGA prototyping board like the Terasic DE0-nano, capable of running a complete 32-bit System-on-Chip for around £50. Even larger boards with the memory capacity to bring up a full Linux system on the design cost a few hundred pounds.

In this talk Julius Baxter and Jeremy Bennett will present the OpenRISC architecture and OpenRISC Reference Platform SoC (ORPSoC), and show how to take this open source design and get it running on an FPGA board.

This is a practical evening, aimed at users who have never done any chip design. Using a Xilinx ML501 prototyping board, Julius Baxter will demonstrate all the steps from obtaining the initial hardware design through to bringing up the board and booting a full Linux system.

The following topics will be covered:

  • an overview of OpenCores and the OpenRISC project
  • an introduction to the Verilog Hardware Design Language
  • how to synthesize the design into a FPGA bitstream
  • what needs modifying to run on different boards
  • how to get software running
  • porting a simple (newlib) library to the board
  • demonstration of Linux booting

Note that this will be an interactive session, and participants are encouraged to bring along their own FPGA dev boards and laptops and to join in, should they wish. If you have a board that is not listed as having a preconfigured ORPSoC build, or you have any other questions concerning the practicalities of this, you should direct your question to the OSHUG discussion list.

Julius Baxter has been involved with the OpenRISC project for 4 years, and during that time he's worked on everything from processor Verilog RTL to the Linux kernel port. After finishing undergraduate studies in his native Australia, he then studied a System-on-Chip design Master's at KTH in Stockholm, Sweden, while working at ORSoC AB - the owners and operators of OpenCores.org. Now living and working Cambridge, Julius maintains a role as an active developer and maintainer on the OpenRISC project, largely dealing with RTL, toolchain and architecture work.

Dr Jeremy Bennett is Chief Executive of Embecosm which provides open source services, tools and models to facilitate embedded software development with complex systems-on-chip. He has been involved with OpenCores for the past decade, and is responsible for much of the software tool chain. Contact him at jeremy.bennett@embecosm.com.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt.

Sponsored by:

Practical System-on-Chip (Program your own open source FPGA SoC)

via OSHUG

At the ninth OSHUG meeting we were given an introduction to FPGA development, and to the OpenCores community and the OpenRISC 1000 open source processor family. At the seventeenth OSHUG meeting we will be given a comprehensive introduction to the practicalities of programming your own open source FPGA system-on-chip.

How to Program Your Own Open Source FPGA System-on-Chip

It is possible to buy a FPGA prototyping board like the Terasic DE0-nano, capable of running a complete 32-bit System-on-Chip for around £50. Even larger boards with the memory capacity to bring up a full Linux system on the design cost a few hundred pounds.

In this talk Julius Baxter and Jeremy Bennett will present the OpenRISC architecture and OpenRISC Reference Platform SoC (ORPSoC), and show how to take this open source design and get it running on an FPGA board.

This is a practical evening, aimed at users who have never done any chip design. Using a Xilinx ML501 prototyping board, Julius Baxter will demonstrate all the steps from obtaining the initial hardware design through to bringing up the board and booting a full Linux system.

The following topics will be covered:

  • an overview of OpenCores and the OpenRISC project
  • an introduction to the Verilog Hardware Design Language
  • how to synthesize the design into a FPGA bitstream
  • what needs modifying to run on different boards
  • how to get software running
  • porting a simple (newlib) library to the board
  • demonstration of Linux booting

Note that this will be an interactive session, and participants are encouraged to bring along their own FPGA dev boards and laptops and to join in, should they wish. If you have a board that is not listed as having a preconfigured ORPSoC build, or you have any other questions concerning the practicalities of this, you should direct your question to the OSHUG discussion list.

Julius Baxter has been involved with the OpenRISC project for 4 years, and during that time he's worked on everything from processor Verilog RTL to the Linux kernel port. After finishing undergraduate studies in his native Australia, he then studied a System-on-Chip design Master's at KTH in Stockholm, Sweden, while working at ORSoC AB - the owners and operators of OpenCores.org. Now living and working Cambridge, Julius maintains a role as an active developer and maintainer on the OpenRISC project, largely dealing with RTL, toolchain and architecture work.

Dr Jeremy Bennett is Chief Executive of Embecosm which provides open source services, tools and models to facilitate embedded software development with complex systems-on-chip. He has been involved with OpenCores for the past decade, and is responsible for much of the software tool chain. Contact him at jeremy.bennett@embecosm.com.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt.

Sponsored by:

Chips (Programmable Logic, Computer Conservation with FPGAs, OpenCores & OpenRISC 1000)

via OSHUG

Programmable logic, and in particular field-programmable gate arrays (FPGAs), is a topic that has frequently come up at OSHUG meetings, both in informal discussion and in presentations (see use of FPGAs in projects covered at OSHUG #5 & OSHUG #8).

This is a particularly exciting technology in the context of open source hardware, as it presents an opportunity to realise performance gains approaching those that are associated with custom silicon – an Application-Specific Integrated Circuit (ASIC) - albeit without the enormous foundry start-up costs which make this largely the reserve of major industry. Furthermore, the design artefacts lend themselves to collaborative development and can be handled in a manner similar to that employed with the source code to computer software.

At the ninth OSHUG meeting we will be given an introduction to programmable logic and the associated development cycle, we'll hear about applications in computer conservation, and we will learn about open source chip design, the OpenCores community and the MIPS-like OpenRISC 1000 CPU.

A Brief Introduction to Programmable Logic

Programmable Logic Devices - mainly FPGAs – are frequently utilised in high speed and computationally intensive applications, and with modern devices containing several million transistors and many gigabits/second of connectivity they are becoming increasingly popular in the race to achieve exascale computing power.

But what does this all mean and how can FPGAs achieve this processing power? How do they differ from the good old CPUs we have in our everyday computers?

In essence, an FPGA is a device that contains configurable blocks of logic along with flexible interconnect between these blocks. They can be configured to contain exactly and only those operations that appear in the algorithms employed in a particular application, which can potentially give them quite a bit of an advantage in terms of throughput and efficiency when compared to static instruction set processors such as a traditional x86 CPU.

In this short introductory talk we will cover the basics of programmable logic devices and talk about the design, synthesis, simulation, implementation and programming cycles associated with FPGA projects.

Omer Kilic is a research student at the University of Kent working on dynamically reconfigurable architectures and embedded systems. When he is not busy working on his PhD project (a reconfigurable heterogeneous computing framework) or running lab classes, he enjoys tinkering and drinking good beer.

Computer Conservation with FPGAs

Having acquired an IBM System/360 Model 30 mainframe whilst he was at university, Lawrence Wilkinson brought it back to life, then abandoned it when the rent and power costs became a drain, and has since felt very guilty. As they became obsolete in the early 1970s, very few IBM System/360s now exist in running order. To make amends he embarked on a project of re-creating the Model 30 as a gate-level simulation, using the original circuits and microcode. While the software-based Hercules emulator is available to run all 360 and 370 software, Lawrence's programmable logic-based solution faithfully replicates the Model 30 with its limited storage and I/O capability, and provides a front panel interface. The basic CPU is implemented in a Xilinx S3 FPGA and the VHDL is available for download under the GPL. Development of the project continues with the further addition of storage and I/O devices.

Lawrence Wilkinson started out as an Electrical and Electronic Engineer in Auckland in the 1980s, transmogrified into an IT and Accounting support person in the late 80s, then went back to hardware and low-level software upon moving to England in the mid 90s. Eventually ending up with the new BAR Formula 1 team, he spent a few years writing and supporting on-car control software, won the World Championship with Brawn Grand Prix in 2009, and currently supports various factory test systems for Mercedes-Benz Grand Prix in Northamptonshire.

OpenCores, Chip Design and the OpenRISC 1000

Opencores dates back to 1999 as a forum for open source chip designs, primarily intended for FPGA, but also used in ASIC. It now hosts several hundred designs, and has over 100,000 registered users world wide.

This talk will look at what is involved in putting together an open source chip design. In particular the licensing issues represent a challenge, with standard F/OSS licenses having serious weaknesses when it comes to licensing hardware.

It will finish with an overview of OpenCores' flagship project, the OpenRISC 1000. This is a 32-bit MIPS-like RISC processor, with a full reference SoC design. It comes with a GNU development tool chain, a number of RTOS ports and an up to date uClibc Linux kernel/BusyBox implementation. In recent years the entire front-end design flow has become open source, as open source electronic design automation (EDA) tools have become available. It has now reached the stage of maturity where some of its development is by commercially funded engineers, as well as a large community of volunteers.

Dr Jeremy Bennett is Chief Executive of Embecosm Limited. Embecosmi provides open source services, tools and models to facilitate embedded software development with complex systems-on chip. He spends two days a month working as the Embedded Systems Champion for the Electronics, Sensors and Photonics KTN, which seeks to improve the flow of knowledge between academia and industry. He can be contacted via jeremy.bennett@embecosm.com.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt.

Chips (Programmable Logic, Computer Conservation with FPGAs, OpenCores & OpenRISC 1000)

via OSHUG

Programmable logic, and in particular field-programmable gate arrays (FPGAs), is a topic that has frequently come up at OSHUG meetings, both in informal discussion and in presentations (see use of FPGAs in projects covered at OSHUG #5 & OSHUG #8).

This is a particularly exciting technology in the context of open source hardware, as it presents an opportunity to realise performance gains approaching those that are associated with custom silicon – an Application-Specific Integrated Circuit (ASIC) - albeit without the enormous foundry start-up costs which make this largely the reserve of major industry. Furthermore, the design artefacts lend themselves to collaborative development and can be handled in a manner similar to that employed with the source code to computer software.

At the ninth OSHUG meeting we will be given an introduction to programmable logic and the associated development cycle, we'll hear about applications in computer conservation, and we will learn about open source chip design, the OpenCores community and the MIPS-like OpenRISC 1000 CPU.

A Brief Introduction to Programmable Logic

Programmable Logic Devices - mainly FPGAs – are frequently utilised in high speed and computationally intensive applications, and with modern devices containing several million transistors and many gigabits/second of connectivity they are becoming increasingly popular in the race to achieve exascale computing power.

But what does this all mean and how can FPGAs achieve this processing power? How do they differ from the good old CPUs we have in our everyday computers?

In essence, an FPGA is a device that contains configurable blocks of logic along with flexible interconnect between these blocks. They can be configured to contain exactly and only those operations that appear in the algorithms employed in a particular application, which can potentially give them quite a bit of an advantage in terms of throughput and efficiency when compared to static instruction set processors such as a traditional x86 CPU.

In this short introductory talk we will cover the basics of programmable logic devices and talk about the design, synthesis, simulation, implementation and programming cycles associated with FPGA projects.

Omer Kilic is a research student at the University of Kent working on dynamically reconfigurable architectures and embedded systems. When he is not busy working on his PhD project (a reconfigurable heterogeneous computing framework) or running lab classes, he enjoys tinkering and drinking good beer.

Computer Conservation with FPGAs

Having acquired an IBM System/360 Model 30 mainframe whilst he was at university, Lawrence Wilkinson brought it back to life, then abandoned it when the rent and power costs became a drain, and has since felt very guilty. As they became obsolete in the early 1970s, very few IBM System/360s now exist in running order. To make amends he embarked on a project of re-creating the Model 30 as a gate-level simulation, using the original circuits and microcode. While the software-based Hercules emulator is available to run all 360 and 370 software, Lawrence's programmable logic-based solution faithfully replicates the Model 30 with its limited storage and I/O capability, and provides a front panel interface. The basic CPU is implemented in a Xilinx S3 FPGA and the VHDL is available for download under the GPL. Development of the project continues with the further addition of storage and I/O devices.

Lawrence Wilkinson started out as an Electrical and Electronic Engineer in Auckland in the 1980s, transmogrified into an IT and Accounting support person in the late 80s, then went back to hardware and low-level software upon moving to England in the mid 90s. Eventually ending up with the new BAR Formula 1 team, he spent a few years writing and supporting on-car control software, won the World Championship with Brawn Grand Prix in 2009, and currently supports various factory test systems for Mercedes-Benz Grand Prix in Northamptonshire.

OpenCores, Chip Design and the OpenRISC 1000

Opencores dates back to 1999 as a forum for open source chip designs, primarily intended for FPGA, but also used in ASIC. It now hosts several hundred designs, and has over 100,000 registered users world wide.

This talk will look at what is involved in putting together an open source chip design. In particular the licensing issues represent a challenge, with standard F/OSS licenses having serious weaknesses when it comes to licensing hardware.

It will finish with an overview of OpenCores' flagship project, the OpenRISC 1000. This is a 32-bit MIPS-like RISC processor, with a full reference SoC design. It comes with a GNU development tool chain, a number of RTOS ports and an up to date uClibc Linux kernel/BusyBox implementation. In recent years the entire front-end design flow has become open source, as open source electronic design automation (EDA) tools have become available. It has now reached the stage of maturity where some of its development is by commercially funded engineers, as well as a large community of volunteers.

Dr Jeremy Bennett is Chief Executive of Embecosm Limited. Embecosmi provides open source services, tools and models to facilitate embedded software development with complex systems-on chip. He spends two days a month working as the Embedded Systems Champion for the Electronics, Sensors and Photonics KTN, which seeks to improve the flow of knowledge between academia and industry. He can be contacted via jeremy.bennett@embecosm.com.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt.