A differential pin pair can be used as a comparator to create a basic ADC. This app note shows how to design a low speed (1 KHz) and “high” speed (50 Khz) ADC technique using only FPGA pins, a resistor and a capacitor. Regardless of whether we ever use this technique, it is illuminating to understand how SAR and Delta Sigma ADCs are constructed:
A simple Analog to Digital Converter can be constructed by adding a small RC circuit to an LVDS input on an FPGA or CPLD…. The LVDS input will act as a simple analog comparator and will output a digital ‘1’ if the Analog Input voltage is higher than the voltage from the RC network. By changing the voltage on the input to the RC circuit, the LVDS comparator can be used to analyze the Analog Input voltage to create an accurate digital representation… A low frequency signal can be processed using a simple Successive Approximation Register… A higher frequency implementation…can be implemented using a Delta Sigma Modulator function, which consists of a sampling register and a Cascade Integrated Comb (CIC) Filter.
Texas instruments has an app note and video explaining how to make a programmable output power supply using a typical LDO voltage regulator and a DAC. This is the technique we used for the Bus Pirate Ultra power supply to get 0.8 to 5volts output, and it works a treat!
Consider the currents going in and out of the VFB node shown in Figure 3, which is connected to the ADJ pin of the LDO. Almost no current flows in or out the device through the ADJ pin (on the order of 0.01µA). As I previously mentioned, the output voltage of the LDO is always produced such that the voltage at the ADJ pin – and therefore the VFB node – is equal to the LDO’s internal reference voltage. Thus, the current through R2 is constant. It follows that any sourcing or sinking of current by the DAC through R3 is reflected as a proportional voltage increase or decrease at VOUT to compensate for the changing current that must flow through R1.
Uses 10 pin 0.5mm flexible PCB connector, wired to the main board with a 1:N connection. This connector is much smaller and thinner than the 1.25mm connector on v1b, it reduces the space needed between the display board and the main board.
Flipped LCD orientation 180 degrees so font data can be written into bounding boxes in a more natural “left-to-right” orientation, eliminating the need to precalculate the text end point and write characters in reverse sequence
Nudged the display towards the IO header. We’ll experiment with some buttons in the remaining available space
Decoupling capacitors on LCD power pins
The 2 inch 240*320 IPS LCD display we’re been testing has a very pleasing pixel density, but we’re also itching to try the bigger 2.8 inch version. Next week we’ll send out a prototype carrier board for the bigger display, as well as some Bus Plug breakout boards.
Bus Pirate prototype Ultra v1b uses an FPGA to process commands sent through a FIFO buffer to a state machine. Pipelined commands can be loaded into the FIFO and executed by the state machine with per-clock repeatability. Non-pipelined commands halt the state machine while the MCU takes over to perform the command, the delay is unpredictable and depends on many factors such as USB operations the MCU may be servicing.
These commands are currently pipelined and handled in the FPGA by the state machine:
Delays (ms, us)
These commands can be pipelined, but are currently handled in registers:
These commands will be pipelined in v1c and later:
ADC reads (on any pin, Vout)
These commands could be pipelined with some hardware updates:
Pull-up resistors toggle
Power supply enable
Power supply margining (by adding an external DAC)
These commands cannot be pipelined because they happen outside the FPGA:
Mode change (reloads the FPGA)
Jump to bootloader
Self-test (involves tests on the MCU and FPGA)
There are also mode macros to consider, which probably need to be a combination of pipelined commands and non-pipelined commands. This week we’ll choose an external DAC and add it to the board.
Bus Pirate prototype “Ultra” v1b successfully wrote to and read back from a 25LC020A SPI EEPROM chip. The image shows the Bus Pirate reading 8 bytes of 0x02 from the EEPROM at address 0x00, and the bus activity can be verified on the logic analyzer graph. Still a long way to go, but it’s nice to have everything working.
Tomorrow we’ll finish the major SPI commands and general purpose mode features like analog measurement and manipulation of the auxiliary pins. As always, you can follow our latest progress in the forum.
Bus Pirate prototype “Ultra” version 1c is technically done, but we came up with some hot last minute additions this weekend. We’ll skip this board and send out the updated version 1d with the additional features at the end of the week.
Version 1c changes:
4 layer PCB
1MHz 12 bit SPI ADC connected directly to the FPGA
Vout/Vref is also measured through the analog multiplexer, which is changed to to the bigger 16bit version (74HCT4067). This will probably change to two 74HCT4051s instead because supplies of the 4067 are skimpy! We can have one “divide by two” 4051 for 5volt measurements on the IO pins, and one 3.3volt 4051 tied directly to the ADC for measuring lower voltage analog stuff
Beefier 3.3volt supply
The 1.2volt supply is now monitored by the MCU for self testing
0.5mm flex cable connector for the display board opens up a bit of board space
Additional ADC measurement point before the back-current shut down protection on the power supply. This gives us a way to include it in the self test and detect when it activates