How big is it ? For starters, the 8-bit adder module is about 300mm (a foot) long – and he’s using five of them. When fully complete, it will stretch 14m wide and stand 2m tall, filling a 30 sq.m room, consisting of seven individual frames that form the parts of the Megaprocessor.
The original plan was for nine frames but he’s managed to squeeze all parts in to seven, building three last year and adding the other four since then. Assembling the individual boards (gates), putting them together to form modules, then fitting it all on to the frames and putting in almost 10kms of cabling is a slow, painstaking job, but he’s been on fire last few months. He has managed to test and integrate the racks shown here and even run some code.
The Megaprocessor has a 16-bit architecture, seven registers, 256bytes of RAM and a questionable amount of PROM (depending on his soldering endurance, he says). It sips 500W, most of it going to light up all the LED’s. He guesses it weighs about half a ton. The processor uses up 15,300 transistors and 8,500 LED’s, while the RAM has 27,000 transistors and 2,048 LED’s. That puts it somewhere between the 8086 and the 68000 microprocessors in terms of number of transistors. He recently got around to calculating the money he’s spent on this to date, and it is notching up over 40,000 Quid (almost $60,000 USD)! You can read a lot of other interesting statistics on the Cost and Materials page.
And kudos to his crazy Ninja skills to notch up just a few failed, bad solder joints, out of a total of over 250,000, and one dead transistor from among almost 42,000. A few cable crimping issues were the least of his troubles. The worst part was when he received a wrong batch of 4000 transistors (correct purchase order, correct packing list, but wrong parts bagged). He realized the problem after soldering all of them, setting him back by quite a bit. He didn’t bother de-soldering them but instead just built fresh replacement boards. He also built a hardware/software simulator for the Megaprocessor using an FPGA board to help him validate his design. Among the first programs he created were a few games (obviously) – Tetris, Tic-Tac-Toe, Life – for which he needed a suitable input device. So he modded a Venom Arcade stick which usually expects itself to be connected to a PlayStation via USB. He says it was “a very civilized thing to mod”.
There is a LOT more interesting stuff to read on his detailed blog posts, so go grab a supply of Coffee, switch off your Phone, and settle in for a few hours diving in to his crazy-awesome build. “This is nuts” said [Clovis Fritzen], who sent in this tip via the BBC News website. Thanks, and we’d agree with his assessment. Check out a couple of videos of the Megaprocessor in action below.
Andy Brown has designed and built a frequency counter using an FPGA, STM32F072 and an Android GUI – the Nanocounter:
After studying the above counting methods I decided on the following goals for my frequency counter, which I’m going to call Nanocounter.
Very accurate measurement over a range of 1 to 50MHz. This would cover the range of MCU crystals that I’d want to measure.
Onboard accurate, but cost effective reference with the option to feed in an external reference clock source.
Advanced options including data logging, charting and calibration of the onboard reference.
That should do for starters, let’s see how I get on. This project will call upon a large number of engineering disciplines including circuit design, PCB layout, SMD reflow, FPGA design, C++ programming and java android programming so I should be in for a fun time.
We have talked about a whole slew of logic and interconnect technologies including TTL, CMOS and assorted low voltage versions. All of these technologies have in common the fact that they are single-ended, i.e. the signal is measured as a “high” or “low” level above ground.
This is great for simple uses. But when you start talking about speed, distance, or both, the single ended solutions don’t look so good. To step in and carry the torch we have Differential Signalling. This is the “DS” in LVDS, just one of the common standards throughout industry. Let’s take a look at how differential signaling is different from single ended, and what that means for engineers and for users.
Collectively, standards like TTL, CMOS, and LVTTL are known as Single Ended technologies and they have in common some undesirable attributes, namely that ground noise directly affects the noise margin (the budget for how much noise is tolerable) as well as any induced noise measured to ground directly adds to the overall noise as well.
By making the voltage swing to greater voltages we can make the noise look smaller in proportion but at the expense of speed as it takes more time to make larger voltage swings, especially with the kind of capacitance and inductance we sometimes see.
Enter Differential Signaling where we use two conductor instead of one. A differential transmitter produces an inverted version of the signal and a non-inverted version and we measure the desired signal strictly between the two instead of to ground. Now ground noise doesn’t count (mostly) and noise induced onto both signal lines gets canceled as we only amplify the difference between the two, we do not amplify anything that is in common such as the noise.
LVDS, CML, and LVPECL
There are various standards with the more common ones being Low Voltage Differential Signaling EIA/TIA-644 (LVDS), Current Mode Logic (CML) and Low Voltage Positive Emitter Coupled Logic (LVPECL). Other examples of Differential Signaling in general include the older RS-422/485 which was used to extend the range of the common single ended signaling known as RS-232, (the “standard” serial port).
LVDS is also used in Serial ATA (SATA), Firewire, gigabit Ethernet and PCIe as well as often being used to communicate to LCD panels. CML is the underlying technology of HDMI and uses current flow instead of voltage as the name implies.
A quick way to demonstrate an LVDS signal is to utilize the fact that the outputs of many FPGA’s and CPLD’s are programmable as to the type of interface standard.
CPLD/FPGA as a Demo
First we create a quick counter right off of the 25Mhz master clock, I used a schematic entry for the top level:
I created lots of different outputs to give myself options while making the video but ultimately just used a clocked version of the 25Mhz.
Next we go to the Assignment Editor for the part and simply select LVDS as the pin type. By selecting one pin it automatically assigns the pair to complete the Differential path.
In this CPLD there is really just one differential standard to select (LVDS complete). Other CPLDs/FPGAs may have a wider selection and may require the use of external resistors or other components depending on the device and selected standard. They may also require the use of the same standard in a block of pins or along one whole side of the part.
Shown here is the PCB schematic showing the pin assignment with the insert showing the ribbon cable pin-out for differential signals. Note the ground connections interspersed between differential pairs on the 30 pin ribbon cable connector.
The LVDS standard is to develop 350mv across the resistor at the end of the path known as the termination resistor. This value is chosen to best match the impedance of the signal path, with values between 100-120 Ohms typical for cables and PCB layout. As speeds go up we get real serious about calculating and controlling the impedance throughout the entire path.
On the example on the workbench shown here there is no receiver, just the termination resistor. At these speeds and in this type of application it is best to dispense with a long ground lead on the scope probe, the slid-on ground clip is shown here instead.
Using the oscilloscope’s built in math function I can simulate what happens in a differential receiver by subtracting one signal from another. Anything common to both, sometimes called common mode noise or a common mode component, is canceled out by this subtraction. In the case where radiated noise is impinged upon both conductors equally , the noise cancellation works well. To this end, techniques such as twisting the cable conductors is common, with the more twists per inch offering better noise reduction but with increased cost, weight, and reduction in flexibility.
Seen here the individual traces are shown and then overlaid, and then the difference taken, with the final reconstructed waveform in red.
Bear in mind that we are talking about just the physical signaling here and does not cover encoding scheme where transitions are minimized, or the clock and signaling is embedded in the data flow.
To optimize high speed performance or to assist in converting from one standard to another, DC blocking may be employed through use of capacitors in series with the data stream. DC blocking also allows the receiver to operate right in the DC bias area that is best for it to reduce noise and things like “jitter” which is a variable delay in the signal.
Removing the DC component, i.e. AC coupling the signal, comes at a price however. AC coupling requires that the signal always be seen as in motion or making transitions on a regular basis.
In the case of an encoding scheme that represents a logical “1” by a transition of the signal and a “0” by no transition, AC coupling then requires that a minimum of transition occur every so often so that the DC baseline of the signal doesn’t drift off. Without AC transitions coupling through the series capacitors driving the input from a high to a low, the voltage would decay and drift towards a unusable value.
An 8b/10b encoding scheme uses 10 bit symbols to represent 8 bits of data while “stuffing” some transitions into the flow so that too much time doesn’t pass without a transition. Telco’s have been using the schemes for many years for sending information over long distances of twisted pair wire using differential signals.
Off the Shelf
There is wide range of discrete drivers and receivers in the various technologies and as you would expect, the vendors’ web pages provide excellent product selection tools. In the old days we had to read or at least glance at every databook on the subject at least once and then narrow down the search by carefully digesting the specifications. Here is TI’s excellent selector that also includes what used to be National Semi:
As you would expect in this day there is a large amount of data available on the Internet. One of my favorites is the LVDS Owner’s Manual which is available from many vendors. I keep a printed copy of this in my lab.
Hopefully this starts to put a tool in your toolbox: If you need to go fast, far or through a noisy environment then consider Differential Signaling.
I’ve been thinking about building stuff with FPGA’s for a while, and usually get turned away because FPGA’s are considerably harder to implement than microcontrollers since they have no on-chip memory. It is necessary to re-program the gates every time they power up, which requires an external flash memory chip. There aren’t great references online for the DIY community, so I figured I’d post how to get this working. Not using dev boards opens a world of opportunities, so I’m a proponent of not using Arduino’s and their FPGA equivalent for too long (sure, they’re good to get started with, but don’t become dependent)
Not wanting to screw up an expensive complex board by being a first-timer at putting an FPGA into a circuit, I figured I’d build a little test board with the cheapest Spartan 6 you can get (about $10), which comes in a solderable TQFP144 package. Sadly, most high end FPGA’s are BGA and therefore quite hard to solder as a DIY project.
This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing.
Part 10 was supposed to be a very big part, with a special surprise of TPU working with a cool peripheral device, but that work is still ongoing. It’s taking a long time to do, mostly due to being busy myself over the past few weeks. However, in this update, I’ll look at bringing interrupts to TPU, as well as fixing an issue with the embedded ram that was causing bloating of the synthesized design.
As you may recall from previous columns, I tend to think of Silego’s
GPAK chips as being super-small mixed-signal FPGAs that you can
literally design and program in just a few minutes, and that cost only a
few cents each.
The idea was that Embedded.com and EETimes.com community members would email me to excite me and delight me with descriptions of the amazing hobby or work projects they might use GPAK4 devices for, thereby convincing me that they deserved to receive one of these little beauties.
Two weeks later, I sauntered into the Pleasure Dome (my office), ensconced myself in my Supreme Commander’s Chair with its super-soft cuddly cushion, and selected the 25 entries that most ignited my imagination and whipped my creative juices into a frenzy (see 25 Free Silego development kits will soon be winging their way).
After this, things went quiet for a while, until earlier today when I heard from one of the lucky recipients, J.R. Stoner, who is principal engineer (and self-described “chief bottle-washer”) at the Bifrost Development Group.
In his email, J.R enclosed the .gp4 (GPAK4) design file associated with his latest project, which is a multi-peripheral controller (click here to download a compressed ZIP file containing the .gp4 design file along with the images presented below). The schematic for the portion of the design featuring the GPAK4 chip (a 20-pin SLG46620 device) is shown below.