Tag Archives: fpga

Designing a CPU in VHDL

via Dangerous Prototypes


A detailed guide on designing a CPU in VHDL by Domipheus:

This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I’d recommend they are read before continuing.
Part 10 was supposed to be a very big part, with a special surprise of TPU working with a cool peripheral device, but that work is still ongoing. It’s taking a long time to do, mostly due to being busy myself over the past few weeks. However, in this update, I’ll look at bringing interrupts to TPU, as well as fixing an issue with the embedded ram that was causing bloating of the synthesized design.

Check out the previous parts at Domipheus Labs.


Implementing a multi-peripheral controller using a tiny mixed-signal FPGA

via Dangerous Prototypes


Max Maxfield over at the Embedded.com writes:

As you may recall from previous columns, I tend to think of Silego’s
GPAK chips as being super-small mixed-signal FPGAs that you can
literally design and program in just a few minutes, and that cost only a
few cents each.

Well, the folks at Silego were so excited by the interest my columns generated within the Embedded.com and EETimes.com communities that they decided to offer 25 development kits for free (see Want a free Silego GPAK4 mixed-signal FPGA development kit?).

The idea was that Embedded.com and EETimes.com community members would email me to excite me and delight me with descriptions of the amazing hobby or work projects they might use GPAK4 devices for, thereby convincing me that they deserved to receive one of these little beauties.

Two weeks later, I sauntered into the Pleasure Dome (my office), ensconced myself in my Supreme Commander’s Chair with its super-soft cuddly cushion, and selected the 25 entries that most ignited my imagination and whipped my creative juices into a frenzy (see 25 Free Silego development kits will soon be winging their way).

After this, things went quiet for a while, until earlier today when I heard from one of the lucky recipients, J.R. Stoner, who is principal engineer (and self-described “chief bottle-washer”) at the Bifrost Development Group.

In his email, J.R enclosed the .gp4 (GPAK4) design file associated with his latest project, which is a multi-peripheral controller (click here to download a compressed ZIP file containing the .gp4 design file along with the images presented below). The schematic for the portion of the design featuring the GPAK4 chip (a 20-pin SLG46620 device) is shown below.

More details at Bifrost Development Group and Embedded.com.

Mesa-Video: 800×600 digital video for Arduinos over 2-wire serial Mesa-Bus

via Dangerous Prototypes


kevinhub88 writes:

This post describes Mesa-Video, a low cost, low power, small size and fully Open Source Hardware and Software solution for providing 800×600 digital video for Arduino ( and other ) microcontrollers.  Mesa-Video makes it quick and easy to display text and 24bit color graphics from any MCU using a single UART serial port pin. Applications for Mesa-Video are embedded projects requiring video output and embedded developers wanting real time visibility into their system operation. Mesa-Video is the 1st of multiple Mesa-Modules planned.

More details at Black Mesa Labs site.

App note: Implementing a TMDS video interface in the Spartan-6 FPGA

via Dangerous Prototypes


Implementing a TMDS video interface in the Spartan-6 FPGA, an app note here (PDF!) from Xilinx:

The DVI and HDMI protocols use TMDS at the physical layer. The TMDS throughput is a function of the serial data rate of the video screen mode being transmitted. This in turn determines the FPGA speed grade that must be used to support this throughput. After the Spartan-3A family, Xilinx has offered embedded electrically-compliant TMDS I/O allowing implementation of DVI and HDMI interfaces inside the FPGA. The operation theory for this is detailed in Video Connectivity Using TMDS I/O in Spartan-3A FPGAs. The data throughput in that application note was maximized at 666 Mb/s in the fastest speed grade. The Spartan-6 FPGA on the other hand has made significant speed improvements. Table 1 shows the maximum throughput for each speed grade of the Spartan-6 FPGA.

Chips Pt.2 (Chip Design for Teenagers, Cocotb, lowRISC)


Back in April 2011 we had our first meeting on the theme of open source chip design, and then around one year later we took a closer look at the OpenRISC Reference Platform System-on-Chip. The thirty-sixth meeting will feature talks on chip design for teenagers, an open source verification framework, and a fully open source system-on-chip that will be manufactured in volume.

Silicon Chip Design for Teenagers

These days we expect school students to learn to write code, and teachers are turning to tools like Scratch (for primary education) and Python (for secondary education). But why stick to software languages. Why not teach coding in Verilog and get children to design silicon chips.

Earlier this year Dan Gorringe attended Chip Hack II in Cambridge. Inspired by this he spent two weeks work experience at Embecosm in August 2014 modifying the Chip Hack materials for use by Year 9-11 students. His resulting application note, "Silicon Chip Design for Teenagers", is to be published very shortly by Embecosm.

In this talk, Dan will share his experience of learning silicon chip design, using Verilog for his first serious attempt at coding and encountering Mentor Graphics EDA tools for the first time.

Dan Gorringe has just started year 11 and faces the horrors of GCSE exams in 8 months time, so silicon chip design is just light relief. He has aspirations to a career in computing.

Cocotb, an Open Source Verification Framework

Verifying hardware designs has always been a significant challenge but very few open-source tools have emerged to support this effort. The recent advances in verification to facilitate complex designs often depend on specialist knowledge and expensive software tools. In this talk we will look at Cocotb, an open-source verification framework, and explore whether Python is a viable language for verification.

Chris Higgs has over a decade of experience working with FPGAs in various industries. His software background has shaped his approach to RTL design and verification and he now spends his time trying to bridge the divide between hardware and software development.

lowRISC — a Fully Open Source RISC-V System-on-Chip

The lowRISC project has been formed to produce a System-on-Chip which will be open source right down to the HDL, implementing the open RISC-V instruction set architecture. Volume manufacture of silicon manufacture is planned, along with creating and distributing low-cost development boards. This talk will describe the aims of the lowRISC project, summarise its current status, describe some of the features that are being implemented, and give details on how you can get involved.

Alex Bradbury is a researcher at the University of Cambridge Computer Laboratory where he works on compilation techniques for a novel many-core architecture. He writes LLVM Weekly, is co-author of Learning Python with Raspberry Pi, and has been a contributor to the Raspberry Pi project since the first alpha hardware was available.

Note: Please aim to arrive by 18:15 as the first talk will start at 18:30 prompt.

Sponsored by:

Lightning Talks


For the twenty-fourth OSHUG meeting we've decided to try something new and we will be hosting a series of lightning talks. The first five talks have been confirmed and details of these can be found below. Offers of additional talks of between five and ten minutes are invited and proposals can either be submitted in advance via e-mail or made on the night (please arrive early).

Note that this month the meeting takes place on a Wednesday.

FUNcube Satellite

FUNcube-1 is a UK amateur radio educational satellite that is due to be launched later this year, and that uses open source hardware to bring real-time space based experiments to classrooms around the globe. Three members of the on-board computer team will discuss project goals and progress.

64-core Parallella Prototype

Simon Cook will be demonstrating one of only two 64-core Parallella prototypes in the UK.

PCBmodE — a PCB design tool written in Python around JSON, SVG and Inkscape

Saar Drimer will be talking about an open source PCB design tool, that reads shape and placement information stored in JSON files to produce an SVG graphical representation of them. Routing is drawn with Inkscape, then extracted by PCBmodE and stored in an input JSON file that's used for the next board generation. A post-processor 'gerberises' the SVGs into "Extended Gerbers" (RS-274X) for manufacturing.

Interfacing High-performance Low-cost Embedded Systems with FPGAs

Mustafa H. Yuce will be talking about an open source project that interfaces embedded systems including BeagleBone and Raspberry Pi with FPGAs, to enable the implementation of high-speed parallel processing applications such as computer vision.


Alan Wood will be talking about the recently developed Flux series of boards that are used for motion control applications.

Open Source Junction 4 Report

Paul Tanner will be providing a report from the OSS Watch two day workshop, Open Source Junction 4: Open Source Hardware meets Open Source Software.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt.

Sponsored by: