The Red Pitaya is a credit-card sized board that runs Linux, has Ethernet, and a good bit of RAM. This sounds a lot like a Raspberry Pi and BeagleBone Black, but the similarities end there. The Red Pitaya also has two RF inputs, two RF outputs, and a load of digital IOs, all connected to an Xilinx SoC that includes an FPGA. [Pavel] realized the Pitaya had all the components of a software-defined radio, and built an implementation to prove it.
The input for the SDR taps directly into one of the high impedance inputs with a simple loop antenna made out of telephone cable. The actual software-defined part of this radio borrows heavily from an Xilinx application note, while everything is controlled by either SDR# or HDSDR.
[Pavel] included a pre-built SD card image with all his software, so cloning this project is simply a matter of copying an SD card and building an antenna. The full source is also available, interesting if you would like to muck about with FPGAs and SDRs.
One of the mnemonics you may hear thrown around is DDS which stands for Direct Digital Synthesis. DDS can be as simple as taking a digital value — a collection of ones and zeroes — and processing it through a Digital to Analog Converter (DAC) circuit. For example, if the digital source is the output of a counter that counts up to a maximum value and resets then the output of the DAC would be a ramp (analog signal) that increases in voltage until it resets back to its starting voltage.
This concept can be very useful for creating signals for use in a project or as a poor-man’s version of a signal or function generator. With this in mind I set out here to demonstrate some basic waveforms using programmable logic for flexibility, and a small collection of resistors to act as a cheap DAC. In the end I will also demonstrate an off-the-shelf and inexpensive DDS chip that can be used with any of the popular micro-controller boards available that support SPI serial communication.
All of the topics covered in the video are also discussed further after the break.
I chose to use Programmable Logic (PL) to build the various circuits as it was quick to configure and didn’t require very much construction while being extremely flexible. It also didn’t require any software programming, IDE, target processor board, etc. This might be an interesting project for you if you are interested in learning or exercising some basic Programmable Logic skills, here I use Altera’s free Quartus II Web version and an inexpensive programmer clone. For the first couple of examples I am using a Complex Programmable Logic Device. (CPLD)
Basic Signal Generation
Creating waveforms can also be done with dedicated logic, for example a CD4060 oscillator/counter can be used instead of the PL counter or also a microcontroller with I/O ports could be used. Note that the microcontroller version does better the more assistance it gets from dedicated peripherals such as a timer or a timer/counter that reloads without waiting for the processor to respond and reset it.
Here are two waveforms created with a simple counter and resistors organized as an R/2R ladder. As the output of the counter increments in binary, the resulting voltage divider created by the interconnected resistors and outputs creates consistent steps between each of the counts; 256 in this case due to 8 outputs being used. Taking the most significant bit also demonstrates a symmetrical square wave.
Building Different Signals is Easy
If the counter were to count downwards upon reaching its maximum count instead of resetting to zero, then a triangle waveform would be generated. So far that’s three waveforms using just a counter and some resistors.
On a slightly different topic, using just some I/O lines, an R/2R ladder, and an analog comparator (ala LM339) a basic type of Analog to Digital Converter (ADC) can be made. Don’t misread this, we were talking about going from digital to analog before but now we’re talking about going from analog to digital.
To describe it simply, a processor or digital counter is connected to the R/2R ladder which is connected to the input of an analog comparator. The voltage to be measured is then connected to the other input of the comparator and then the counter proceeds to count up until the R/2R ladder voltage equals or exceeds the voltage being measured. At that time the comparator trips and the equivalent digital value of the analog voltage being measured is represented by the counter value feeding the R/2R ladder.
Assuming that the voltage to be measured is somewhat stable, the process can be repeated to track the voltage as it (slowly) changes or the count can be reversed until the comparator clears and then reverses. This might be useful for measurements such as monitoring a battery voltage level, etc.
While continuing the use of an adjunctive comparator, a simple voltage to frequency converter can be made by having the counter change directions when the comparator trips. This is not a perfect converter (nothing I do is perfect, life and engineering is a compromise) as very notably the amplitude of the triangle waveform changes in amplitude, but a full voltage square wave would be easy to generate.
Basic Principles for Sine Wave Generation
Finally we can create a sinewave through the addition of a look-up-table that contains the appropriate data to approximate a mathematical sine function. A look-up-table (LUT) is simply a piece of memory such as Read Only Memory (ROM) in series with the data, in our case the incrementing counter represents an incrementing address, and the data output is the result of a pre-calculated Sine table.
For this I have switched to a Field Programmable Gate Array (FPGA) which has better internal memory and the ability to initialize the memory with the contents of the Sine table I created for the LUT. In the schematic for the interior of my FPGA the LUT can be seen off to the right just in front of the output pins.
Programming Complex Waveforms
One advantage of a Sine wave created by DDS is that it can be generated at a wide range of frequencies and keep its same shape (low distortion).
Just for fun and to demonstrate something that can done easily with DDS I created a non-symmetrical waveform. Looking carefully you can see two cycles of square wave, two of ramp and then two of sine wave. Any waveform that can be “drawn” in memory can be created this way.
Other DDS Hardware Options
And finally, if you need a DDS without the muss and fuss of making it out of components yourself, there is a selection of DDS components available that are low cost and accurate. Shown here is an Analog Devices 9387 in an evaluation board from the manufacturer. It is SPI serial interface driven and so can be connected to most available single board controllers.
Varying the frequency and phase of a signal by microprocessor control is integral to a DDS system. The software that comes with the evaluation the board shows that two frequencies and two phase offsets can be stored allowing Frequency Shift Keying (FSK) and Phase Shift Keying (PSK) as well as sweeping between two frequencies. This is a useful capability, for example the frequency response of a circuit such as a filter can be observed by sweeping a frequency on the input and then measuring the output on an oscilloscope.
If you want to know more about DDS there is a lot of information available on manufacturer’s websites and the Internet. Advanced topics to search for include embedded sub-modulation and use with phase lock loops to reduce phase noise, up-conversion using multipliers, and other synthesis circuits used in RF telecommunications.
Thanks to the worldwide proliferation of smartphones, tiny high-resolution displays are common and cheap. Interfacing these displays with anything besides a phone has been a problem. [twl] has a board that does just that, converting HDMI to something these displays can understand, and providing a framebuffer so these displays can be written to through small microcontrollers.
[twl] is using a rather large FPGA to handle all the conversion from HDMI to the DSI the display understands. He’s using an Xilinx Spartan-6-SLX9, one of the most hobbyist friendly devices that is able to be hand soldered. Also on the board is a little bit of SDRAM for a framebuffer, HDMI input, and a power supply for the LCD and its backlight.
On the things [twl] has in his ‘to-do’ list, porting Doom to run on a cellphone display is obviously right at the top. He also wants to test the drawing commands for the Arduino side of his board, allowing any board with the suffix ~’ino to paint graphics and text on small, cheap, high-resolution displays. That’s a capability that just doesn’t exist with products twice [twl]‘s projected BOM, and we can’t wait to see what he comes up with.
You can check out the demo video of [twl]‘s board displaying the output of a Raspberry Pi below. If you look very closely, you’ll notice the boot/default screen for the display adapter is the Hackaday Jolly Wrencher.
These days we expect school students to learn to write code, and teachers are turning to tools like Scratch (for primary education) and Python (for secondary education). But why stick to software languages. Why not teach coding in Verilog and get children to design silicon chips.
Earlier this year Dan Gorringe attended Chip Hack II in Cambridge. Inspired by this he spent two weeks work experience at Embecosm in August 2014 modifying the Chip Hack materials for use by Year 9-11 students. His resulting application note, "Silicon Chip Design for Teenagers", is to be published very shortly by Embecosm.
In this talk, Dan will share his experience of learning silicon chip design, using Verilog for his first serious attempt at coding and encountering Mentor Graphics EDA tools for the first time.
Dan Gorringe has just started year 11 and faces the horrors of GCSE exams in 8 months time, so silicon chip design is just light relief. He has aspirations to a career in computing.
Cocotb, an Open Source Verification Framework
Verifying hardware designs has always been a significant challenge but very few open-source tools have emerged to support this effort. The recent advances in verification to facilitate complex designs often depend on specialist knowledge and expensive software tools. In this talk we will look at Cocotb, an open-source verification framework, and explore whether Python is a viable language for verification.
Chris Higgs has over a decade of experience working with FPGAs in various industries. His software background has shaped his approach to RTL design and verification and he now spends his time trying to bridge the divide between hardware and software development.
lowRISC — a Fully Open Source RISC-V System-on-Chip
The lowRISC project has been formed to produce a System-on-Chip which will be open source right down to the HDL, implementing the open RISC-V instruction set architecture. Volume manufacture of silicon manufacture is planned, along with creating and distributing low-cost development boards. This talk will describe the aims of the lowRISC project, summarise its current status, describe some of the features that are being implemented, and give details on how you can get involved.
Alex Bradbury is a researcher at the University of Cambridge Computer Laboratory where he works on compilation techniques for a novel many-core architecture. He writes LLVM Weekly, is co-author of Learning Python with Raspberry Pi, and has been a contributor to the Raspberry Pi project since the first alpha hardware was available.
Note: Please aim to arrive by 18:15 as the first talk will start at 18:30 prompt.
Nearly a year ago, an extremely interesting project hit Kickstarter: an open source GPU, written for an FPGA. For reasons that are obvious in retrospect, the GPL-GPU Kickstarter was not funded, but that doesn’t mean these developers don’t believe in what they’re doing. The first version of this open source graphics processor has now been released, giving anyone with an interest a look at what a late-90s era GPU looks like on the inside, If you’re cool enough, there’s also enough supporting documentation to build your own.
A quick note for the PC Master Race: this thing might run Quake eventually. It’s not a powerhouse. That said, [Bunnie] had a hard time finding an open source GPU for the Novena laptop, and the drivers for the VideoCore IV in the Raspi have only recently been open sourced. A completely open GPU simply doesn’t exist, and short of a few very, very limited thesis projects there hasn’t been anything like this before.
Right now, the GPL-GPU has 3D graphics acceleration working with VGA on a PCI bus. The plan is to update this late-90s setup to interfaces that make a little more sense, and add DVI and HDMI output. Not bad for a failed Kickstarter, right?
Flappy Bird has been ported to just about every system imaginable, including but not limited to the Apple II, Commodores, pretty much every version of the Atari, and serves as a really great demonstration of the TI-99’s graphics capabilities. Porting is one thing, but having a computer automate Flappy Bird is another thing entirely. [Ankur], [Sai], and [Ackerly] in [Dr. Bruce Land]‘s advanced microcontroller design class at Cornell have done just that. They’re playing Flappy Bird with a camera, FPGA, and a penny wired up to a GPIO pin to guide the little 8-bit-bird through Mario pipes.
The setup the team is using consists of a webcam that records the screen of a smartphone, an FPGA, and a little bit of circuitry to emulate screen taps. Inside the FPGA, the team is looking at the video stream from the phone to detect the bird, pipes, and gaps. The ‘tapper’ unit is a US penny, placed right above the ‘tap’ button, wired to a GPIO port. This was found to be the ideal contact for a capacitive touch screen – taps that were too small weren’t registered, and taps that were too big registered as two taps.
For spending an entire semester on automating Flappy Bird, the team has a lot of knowledge to show for it, but not the high score: the bird only makes it through the first pipe 10% of the time, and the second pipe 1% of the time. The high score is three. That’s alright – getting the algorithm right to play the game correctly was very, very difficult, and to nail that problem down, they estimate it would take at least another semester.
The development board being used for this online course is an Altera EMP3032 CPLD conveniently included in the Introduction to FPGA and CPLD kit used in this course. It’s not a powerful device by any measure; it only has 32 macrocells and about 600 usable gates. You won’t be designing CPUs with this thing, but you will be able to grasp the concept of designing logic with code.
Future lessons include building binary counters, PWM-controlled LEDs, and a handheld LED POV device. In any event, it’s a great way to learn about how programmable logic actually works, and a fairly cheap way to get into the world of FPGAs and CPLDs. Introductory video below.
Now that [Bunnie]‘s open hardware laptop – the Novena – is wrapping up its crowdfunding campaign, it only makes sense that development around the Novena project would move over to the more interesting aspects of a completely hackable laptop. The Novena has a huge FPGA on board, with 2 Gbit of very fast memory hanging off it. Also, every single signal pin of the FPGA is broken out on high-speed connectors, making for some very, very interesting possible add-on boards. [Bunnie] has always wanted a portable, high-end oscilloscope to carry with him, and with the new oscope module, he has something that blows out of the water every scope priced below a thousand dollars.
The oscilloscope module [Bunnie] is working on has either two 8-bit channels at 1 GSPS or one 8-bit channel at 2 GSPS with an analog bandwidth of up to 900MHz. The module also has 10 digital channels, so if you need a logic analyzer, there you go.
Being a fairly high-end scope, the hardest part of engineering this scope is the probes. The probes for fast, high-end scopes cost hundreds of dollars by themselves, so [Bunnie] looked for a clean-sheet redesign of the lowly oscope probe. To connect the probe to the module, [Bunnie] realized a SATA cable would be a great solution; they’re high bandwidth, support signals in the GHz range, and are rated for thousands of insertions. These active probes can be combined with a number of front ends for application specific probes – digital probes, ones for power signature analysis, and ones for capturing signals across small loops of wire.
The module itself isn’t quite ready for production yet, but by the time the Novena crowdfunding campaign starts shipping, [Bunnie] will probably be working on the next add-on module for his crazy awesome laptop.
The guys over at hackshed have been busy. [Carl] is making programmable logic design easy with an 8 part CPLD tutorial. Programmable logic devices are one of the most versatile hardware building blocks available to hackers. They also can have a steep learning curve. Cheap Field Programmable Gate Arrays (FPGA) are plentiful, but can have intricate power requirements. Most modern programmable logic designs are created in a Hardware Description Language (HDL) such as VHDL or Verilog. Now you’ve got a new type of device, a new language, an entirely new programming paradigm, and a complex IDE to learn all at once. It’s no wonder FPGAs have sent more than one beginner running for the hills.
The tutorial cuts the learning curve down in several ways. [Carl] is using Complex Programmable Logic Devices (CPLD). At the 40,000 foot level, CPLDs and FPGAs do the same thing – they act as re-configurable logic. FPGAs generally do not store their configuration – it has to be loaded from an external FLASH, EEPROM, or connected processor. CPLDs do store their configuration, so they’re ready as soon as they power up. As a general rule, FPGAs contain more configurable logic than CPLDs. This allows for larger designs to be instantiated with FPGAs. Don’t knock CPLDs though. CPLDs have plenty of room for big designs, like generating VGA signals.
[Carl] also is designing with schematic capture in his tutorial. With the schematic capture method, digital logic schematics are drawn just as they would be in Eagle or KiCad. This is generally considered an “old school” method of design capture. A few lines of VHDL or Verilog code can replace some rather complex schematics. [Carl's] simple designs don’t need that sort of power though. Going the schematic capture route eliminates the need to learn VHDL or Verilog.
[Carl's] tutorial starts with installing Altera’s Quartus II software. He then takes the student through the “hardware hello world” – blinking an LED. By the time the tutorial is done, the user will learn how to create a 4 bit adder and a 4 bit subtractor. With all that under your belt, you’re ready to jump into big designs – like building a retrocomputer.
Cheap FPGA boards are readily available, as are VHDL implementations of classic CPUs like the 6502, 6809, and Z80. Up until now, we haven’t seen anyone take these two parts and combine them into a complete system that turns an FPGA board into a complete 8-bit retrocomputer. Thanks to [Grant]‘s work, it’s now possible to do just that (server on fire, here’s a google cache) with a $30 FPGA board and a handful of parts.
In its full configuration, the Multicomp, as [Grant] calls his project, includes either a 6502, 6809, Z80, or (in the future) a 6800 CPU. Video options include either monochrome RCA, RGB VGA, or RGB via SCART. This, along an SD card interface, a PS2 keyboard, and the ability to connect an external 128kB RAM chip (64k available) means it’s a piece of cake to build a proper and complete portable retrocomputer.
What’s extremely interesting about [Grant]‘s project is the fact the data and address lines are fully exposed on the FPGA board. This means it’s possible to add whatever circuit you’d like to whatever retrocomputer you can imagine; if you want a few NES gamepads, an IDE interface, or you’d like to design your own primitive video card, it’s just a matter of designing a circuit and writing some assembly.
If you’d like to build your own, search “EP2C5T144C8N” on the usual sites, grab a few resistors and connectors, and take a look at [Grant]‘s documentation and upcoming examples.
[Valentin] recently tipped us about an FPGA development board he just finished. It is called the FleaFPGA and is aimed to get people interested in the world of Field Programmable Gate Arrays. One of the other reasons that also got [Valentin] to design his own board was that he was frustrated with the existing solutions, them being either too pricey or fairly spare in terms of connectivity.
The main components that you can see in the platform shown above are: a lattice MachX02-7000HE FPGA (6864LUTs), 256Mbits of SDRAM, a USB2.0 host port, a 4096-color VGA connector, a 3.5mm stereo connector, an SD/MMC card slot, a PS/2 keyboard/mouse combo port, a few push buttons and LEDs. An expansion header is also present in order to connect the FleaFPGA to future shields that will be developed. Unfortunately only the board schematics have been released and [Valentin] is currently aiming for a price of $60 per board for <100 quantities. You’ll be able to see a video of the board in action after the break, in which the FPGA has been loaded with a 68000 software core running a variation of the Amiga Juggler Demo.
Unless you’re bit-banging a CRT interface or using a bunch of resistors to connect a VGA monitor to your project, odds are you’re using proprietary hardware as a graphics engine. The GPU on the Raspberry Pi is locked up under an NDA, and the dream of an open source graphics processor has yet to be realized. [Frank Bruno] at Silicon Spectrum thinks he has the solution to that: a completely open source GPU implemented on an FPGA.
Right now, [Frank] has a very lightweight 2D and 3D engine well-suited for everything from servers to embedded devices. If their Kickstarter meets its goal, they’ll release their project to the world, giving every developer and hardware hacker out there a complete, fully functional, open source GPU.
The last time [Mark] was at the scrap yard, he managed to find the analogue input and output cards of an old Akai DR8 studio hard drive recorder. These cards offered great possibilities (8 ADC inputs, 12 DAC outputs) so he repaired them and made a whole audio system out of them.
The repair only involved changing a couple of low dropout regulators. Afterwards, [Mark] interfaced one of his CPLD development boards so he could produce some sine waves and digitize signals generated from a PC based audio test unit. He then made the frame shown in the picture above and switched to an Altera Cyclone IV FPGA. To complete his system, he designed a small board to attach a VGA screen, and another to use the nRF24L01 wireless module.
Inside the FPGA, [Mark] used a NIOS II soft core processor to orchestrate the complete system and display a nice user interface. He even made another system with an USB host plug to connect MIDI enabled peripherals, allowing him to wirelessly control his creation.
We’ve been following the work of [Andrew Holme] and his homebrew GPS receiver for a while now. A few years ago, [Andrew] built a four-channel GPS receiver from scratch, but apparently that wasn’t enough for him. He expanded his build last year to track up to eight satellites, and this month added a Raspberry Pi for a 12-channel, battery-powered homebrew GPS receiver that has an accuracy of about 3 feet.
The Raspi is attached to an FPGA board that handles the local oscillator, real-time events, and tracks satellites automatically. The Pi handles the difficult but not time-critical math through an SPI interface. Because the Pi is attached to the FPGA through an SPI interface, it can also load up the FPGA with even more custom code, potentially turning this 12-channel receiver into a 16- or 18-channel one.
An LCD display attached to the FPGA board shows the current latitude, longitude, and other miscellaneous data like the number of satellites received. With a large Li-ion battery, the entire system can be powered for about 5 hours; an impressively portable GPS system that rivals the best commercial options out there.