Tag Archives: fpga

Yellowstone JTAG debugging

via Dangerous Prototypes


A follow-up to the FPGA-based disk controller for Apple II post, Steve writes:

After a month of inactivity, I finally returned to my unfinished Yellowstone disk controller project to investigate the JTAG programming problems. Yellowstone is an FPGA-based disk controller card for the Apple II family, that aims to emulate a Liron disk controller or other models of vintage disk controller. It’s still a work in progress.
Last month I discovered some JTAG problems. With the Yellowstone card naked on my desk, and powered from an external 5V supply, JTAG programming works fine.

More details at Big Mess o’ Wires.

BML USB 3.0 FPGA interface over PMOD

via Dangerous Prototypes


An open-source-hardware USB 3.0 to FPGA PMOD interface design from Black Mesa Labs:

Black Mesa Labs is presenting an open-source-hardware USB 3.0 to FPGA PMOD interface design.  First off, please lower your expectations. USB 3.0 physical layer is capable of 5 Gbps, or 640 MBytes/Sec. This project can’t provide that to your FPGA over 2 PMOD connectors – not even close. It does substantially improve PC to FPGA bandwidth however, 30x for Writes and 100x for Reads compared to a standard FTDI cable based on the FT232 ( ala RS232 like UART interface at 921,600 baud ). A standard FTDI cable is $20 and the FT600 chip is less than $10, so BML deemed it a project worth pursuing.

More details at Black Mesa Labs homepage.

Via the contact form.

BML HDMI video for FPGAs over PMOD

via Dangerous Prototypes

BML HDMIvideoforFPGAs over PMOD

Here are two open-source-hardware HDMI  video boards for adding digital video to FPGA platforms with standard PMOD connectors from Black Mesa Labs:

The BML 3bit HDMI over single-PMOD uses 7 of 8 available LVCMOS 3.3 pins on a single PMOD to provide 3bit color ( R,G,B 100% On or Off ). Example Verilog design drives 800×600 using a 40 MHz dot clock. The TI TFP410 is very versatile in the resolutions it can generate and is really just limited by the clock that the FPGA can provide and the data rates the PMOD connectors are capable of.

More details at Black Mesa Labs homepage.

App note: Choose the right power supply for your FPGA

via Dangerous Prototypes


Designing a power supply for FPGA includes multiple voltage, ripple management and power sequencing, here’s an app note from Maxim Integrated. Link here (PDF)

Field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) require 3 to 15, or even more, voltage rails. The logic fabric is usually at the latest process technology node that determines the core supply voltage. Configuration, housekeeping circuitry, various I/Os, serializer/deserializer (SerDes) transceivers, clock managers, and other functions all have differing requirements for voltage rails, sequencing/tracking, and voltage ripple limits. An engineer must consider all of these issues when designing a power supply for an FPGA.

App note: Clearing Xilinx FPGA configuration to allow boundary scan testing

via Dangerous Prototypes

Another application note from XJTAG on preparing Xilinx FPGA for proper boundary scan testing. Link here

When Xilinx FPGAs are configured it can restrict the boundary scan access to some signals on the device. One work-around for this problem is to configure the FPGA with a ‘blank’ image that closely matches its unconfigured state, allowing boundary scan testing to occur without any problems.

A second issue that can affect boundary scan testing with FPGAs is that they contain pull resistors. Depending on the design, these may be enabled when the FPGA is unconfigured as well as when it is configured. If these internal resistors are enabled on nets that contain pull resistors mounted on the board, two potential problems can occur:

1. If the internal resistor and external resistor pull in opposite directions, the boundary scan tests may not be able to test the external pull resistor if it is weaker than the internal pull resistor.
2. If the internal and external resistors pull in the same direction, a fault with the external resistor may not be detected because the internal resistor may mask the fault.

By setting the correct configuration options it is possible to disable these internal pull resistors when generating a ‘blank’ FPGA image.