Tag Archives: fpga

Chips Pt.2 (Chip Design for Teenagers, Cocotb, lowRISC)

via OSHUG

Back in April 2011 we had our first meeting on the theme of open source chip design, and then around one year later we took a closer look at the OpenRISC Reference Platform System-on-Chip. The thirty-sixth meeting will feature talks on chip design for teenagers, an open source verification framework, and a fully open source system-on-chip that will be manufactured in volume.

Silicon Chip Design for Teenagers

These days we expect school students to learn to write code, and teachers are turning to tools like Scratch (for primary education) and Python (for secondary education). But why stick to software languages. Why not teach coding in Verilog and get children to design silicon chips.

Earlier this year Dan Gorringe attended Chip Hack II in Cambridge. Inspired by this he spent two weeks work experience at Embecosm in August 2014 modifying the Chip Hack materials for use by Year 9-11 students. His resulting application note, "Silicon Chip Design for Teenagers", is to be published very shortly by Embecosm.

In this talk, Dan will share his experience of learning silicon chip design, using Verilog for his first serious attempt at coding and encountering Mentor Graphics EDA tools for the first time.

Dan Gorringe has just started year 11 and faces the horrors of GCSE exams in 8 months time, so silicon chip design is just light relief. He has aspirations to a career in computing.

Cocotb, an Open Source Verification Framework

Verifying hardware designs has always been a significant challenge but very few open-source tools have emerged to support this effort. The recent advances in verification to facilitate complex designs often depend on specialist knowledge and expensive software tools. In this talk we will look at Cocotb, an open-source verification framework, and explore whether Python is a viable language for verification.

Chris Higgs has over a decade of experience working with FPGAs in various industries. His software background has shaped his approach to RTL design and verification and he now spends his time trying to bridge the divide between hardware and software development.

lowRISC — a Fully Open Source RISC-V System-on-Chip

The lowRISC project has been formed to produce a System-on-Chip which will be open source right down to the HDL, implementing the open RISC-V instruction set architecture. Volume manufacture of silicon manufacture is planned, along with creating and distributing low-cost development boards. This talk will describe the aims of the lowRISC project, summarise its current status, describe some of the features that are being implemented, and give details on how you can get involved.

Alex Bradbury is a researcher at the University of Cambridge Computer Laboratory where he works on compilation techniques for a novel many-core architecture. He writes LLVM Weekly, is co-author of Learning Python with Raspberry Pi, and has been a contributor to the Raspberry Pi project since the first alpha hardware was available.

Note: Please aim to arrive by 18:15 as the first talk will start at 18:30 prompt.

Sponsored by:

Lightning Talks

via OSHUG

For the twenty-fourth OSHUG meeting we've decided to try something new and we will be hosting a series of lightning talks. The first five talks have been confirmed and details of these can be found below. Offers of additional talks of between five and ten minutes are invited and proposals can either be submitted in advance via e-mail or made on the night (please arrive early).

Note that this month the meeting takes place on a Wednesday.

FUNcube Satellite

FUNcube-1 is a UK amateur radio educational satellite that is due to be launched later this year, and that uses open source hardware to bring real-time space based experiments to classrooms around the globe. Three members of the on-board computer team will discuss project goals and progress.

64-core Parallella Prototype

Simon Cook will be demonstrating one of only two 64-core Parallella prototypes in the UK.

PCBmodE — a PCB design tool written in Python around JSON, SVG and Inkscape

Saar Drimer will be talking about an open source PCB design tool, that reads shape and placement information stored in JSON files to produce an SVG graphical representation of them. Routing is drawn with Inkscape, then extracted by PCBmodE and stored in an input JSON file that's used for the next board generation. A post-processor 'gerberises' the SVGs into "Extended Gerbers" (RS-274X) for manufacturing.

Interfacing High-performance Low-cost Embedded Systems with FPGAs

Mustafa H. Yuce will be talking about an open source project that interfaces embedded systems including BeagleBone and Raspberry Pi with FPGAs, to enable the implementation of high-speed parallel processing applications such as computer vision.

Flux

Alan Wood will be talking about the recently developed Flux series of boards that are used for motion control applications.

Open Source Junction 4 Report

Paul Tanner will be providing a report from the OSS Watch two day workshop, Open Source Junction 4: Open Source Hardware meets Open Source Software.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt.

Sponsored by:

Practical System-on-Chip (Program your own open source FPGA SoC)

via OSHUG

At the ninth OSHUG meeting we were given an introduction to FPGA development, and to the OpenCores community and the OpenRISC 1000 open source processor family. At the seventeenth OSHUG meeting we will be given a comprehensive introduction to the practicalities of programming your own open source FPGA system-on-chip.

How to Program Your Own Open Source FPGA System-on-Chip

It is possible to buy a FPGA prototyping board like the Terasic DE0-nano, capable of running a complete 32-bit System-on-Chip for around £50. Even larger boards with the memory capacity to bring up a full Linux system on the design cost a few hundred pounds.

In this talk Julius Baxter and Jeremy Bennett will present the OpenRISC architecture and OpenRISC Reference Platform SoC (ORPSoC), and show how to take this open source design and get it running on an FPGA board.

This is a practical evening, aimed at users who have never done any chip design. Using a Xilinx ML501 prototyping board, Julius Baxter will demonstrate all the steps from obtaining the initial hardware design through to bringing up the board and booting a full Linux system.

The following topics will be covered:

  • an overview of OpenCores and the OpenRISC project
  • an introduction to the Verilog Hardware Design Language
  • how to synthesize the design into a FPGA bitstream
  • what needs modifying to run on different boards
  • how to get software running
  • porting a simple (newlib) library to the board
  • demonstration of Linux booting

Note that this will be an interactive session, and participants are encouraged to bring along their own FPGA dev boards and laptops and to join in, should they wish. If you have a board that is not listed as having a preconfigured ORPSoC build, or you have any other questions concerning the practicalities of this, you should direct your question to the OSHUG discussion list.

Julius Baxter has been involved with the OpenRISC project for 4 years, and during that time he's worked on everything from processor Verilog RTL to the Linux kernel port. After finishing undergraduate studies in his native Australia, he then studied a System-on-Chip design Master's at KTH in Stockholm, Sweden, while working at ORSoC AB - the owners and operators of OpenCores.org. Now living and working Cambridge, Julius maintains a role as an active developer and maintainer on the OpenRISC project, largely dealing with RTL, toolchain and architecture work.

Dr Jeremy Bennett is Chief Executive of Embecosm which provides open source services, tools and models to facilitate embedded software development with complex systems-on-chip. He has been involved with OpenCores for the past decade, and is responsible for much of the software tool chain. Contact him at jeremy.bennett@embecosm.com.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt.

Sponsored by:

Practical System-on-Chip (Program your own open source FPGA SoC)

via OSHUG

At the ninth OSHUG meeting we were given an introduction to FPGA development, and to the OpenCores community and the OpenRISC 1000 open source processor family. At the seventeenth OSHUG meeting we will be given a comprehensive introduction to the practicalities of programming your own open source FPGA system-on-chip.

How to Program Your Own Open Source FPGA System-on-Chip

It is possible to buy a FPGA prototyping board like the Terasic DE0-nano, capable of running a complete 32-bit System-on-Chip for around £50. Even larger boards with the memory capacity to bring up a full Linux system on the design cost a few hundred pounds.

In this talk Julius Baxter and Jeremy Bennett will present the OpenRISC architecture and OpenRISC Reference Platform SoC (ORPSoC), and show how to take this open source design and get it running on an FPGA board.

This is a practical evening, aimed at users who have never done any chip design. Using a Xilinx ML501 prototyping board, Julius Baxter will demonstrate all the steps from obtaining the initial hardware design through to bringing up the board and booting a full Linux system.

The following topics will be covered:

  • an overview of OpenCores and the OpenRISC project
  • an introduction to the Verilog Hardware Design Language
  • how to synthesize the design into a FPGA bitstream
  • what needs modifying to run on different boards
  • how to get software running
  • porting a simple (newlib) library to the board
  • demonstration of Linux booting

Note that this will be an interactive session, and participants are encouraged to bring along their own FPGA dev boards and laptops and to join in, should they wish. If you have a board that is not listed as having a preconfigured ORPSoC build, or you have any other questions concerning the practicalities of this, you should direct your question to the OSHUG discussion list.

Julius Baxter has been involved with the OpenRISC project for 4 years, and during that time he's worked on everything from processor Verilog RTL to the Linux kernel port. After finishing undergraduate studies in his native Australia, he then studied a System-on-Chip design Master's at KTH in Stockholm, Sweden, while working at ORSoC AB - the owners and operators of OpenCores.org. Now living and working Cambridge, Julius maintains a role as an active developer and maintainer on the OpenRISC project, largely dealing with RTL, toolchain and architecture work.

Dr Jeremy Bennett is Chief Executive of Embecosm which provides open source services, tools and models to facilitate embedded software development with complex systems-on-chip. He has been involved with OpenCores for the past decade, and is responsible for much of the software tool chain. Contact him at jeremy.bennett@embecosm.com.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt.

Sponsored by:

Goes to Canterbury! (Collaboration, building communities, surface mount adventures)

via OSHUG

For our 11th meeting, we are visiting the School of Engineering and Digital Arts at the University of Kent. Trains run regularly to and from central London and take approximately an hour. For anyone wishing to stay overnight please see the list of accommodation.

Open Source Hardware Collaboration

An assessment of the current state of the art in hardware collaboration through a tour of a series of Open Source Hardware projects. How easy is it to discover projects, view and understand their designs, build your own version and contribute changes back?

Paul Downey (psd) is a doodling software hacker, former member of Osmosoft — a small Open Source software team where he represented BT at the W3C, a co-organiser of OSHUG and a co-founder of SolderPad, a collaboration platform for electronic design.

Building open, communicating communities

The hardware engineering community is typically seen as fragmented, closed and conservative, shackled by the dependency on restrictive closed-source tools. Thankfully, we are now at a time where this is changing. In this talk, Saar Drimer will discuss his efforts to bring the FPGA community together so we can reach the level of sharing and project integration that the open source software community currently enjoys. The end goal is to reach a state where projects are integrated in a similar way to what Linux's package mangers enable: "sudo apt-get ddr2-controller". [Background reading].

Saar Drimer is an experienced hardware engineer. In the past he's hacked the UK's Chip and PIN payment system, and advocated reproducible research practices in the engineering sciences. Now he's working on boldport, an "IndieEDA" company that aims to make HW/FPGA easier.

Adventures in working with surface mount devices

An ambitious open source hardware project--Amino--recently called for Alan Wood to uplift his home lab to support prototyping, testing and basic production using surface mount devices. Alan will be sharing with us some of the things he has learnt, and giving us a run through what you might require in order to tackle working with surface mount devices yourself. Rather than using expensive off-the-shelf tooling, Alan will be covering a number of affordable approaches that make this possible without breaking the bank.

Alan Wood originally trained in systems engineering, got lost in software engineering and open source for a decade, before returning back to his hardware roots via the open source hardware and makers movement that has gathered momentum over the last few years.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt. Parking is available at the Jennison Building, however, please ensure that you are parked within a bay.

Goes to Canterbury! (Collaboration, building communities, surface mount adventures)

via OSHUG

For our 11th meeting, we are visiting the School of Engineering and Digital Arts at the University of Kent. Trains run regularly to and from central London and take approximately an hour. For anyone wishing to stay overnight please see the list of accommodation.

Open Source Hardware Collaboration

An assessment of the current state of the art in hardware collaboration through a tour of a series of Open Source Hardware projects. How easy is it to discover projects, view and understand their designs, build your own version and contribute changes back?

Paul Downey (psd) is a doodling software hacker, former member of Osmosoft — a small Open Source software team where he represented BT at the W3C, a co-organiser of OSHUG and a co-founder of SolderPad, a collaboration platform for electronic design.

Building open, communicating communities

The hardware engineering community is typically seen as fragmented, closed and conservative, shackled by the dependency on restrictive closed-source tools. Thankfully, we are now at a time where this is changing. In this talk, Saar Drimer will discuss his efforts to bring the FPGA community together so we can reach the level of sharing and project integration that the open source software community currently enjoys. The end goal is to reach a state where projects are integrated in a similar way to what Linux's package mangers enable: "sudo apt-get ddr2-controller". [Background reading].

Saar Drimer is an experienced hardware engineer. In the past he's hacked the UK's Chip and PIN payment system, and advocated reproducible research practices in the engineering sciences. Now he's working on boldport, an "IndieEDA" company that aims to make HW/FPGA easier.

Adventures in working with surface mount devices

An ambitious open source hardware project--Amino--recently called for Alan Wood to uplift his home lab to support prototyping, testing and basic production using surface mount devices. Alan will be sharing with us some of the things he has learnt, and giving us a run through what you might require in order to tackle working with surface mount devices yourself. Rather than using expensive off-the-shelf tooling, Alan will be covering a number of affordable approaches that make this possible without breaking the bank.

Alan Wood originally trained in systems engineering, got lost in software engineering and open source for a decade, before returning back to his hardware roots via the open source hardware and makers movement that has gathered momentum over the last few years.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt. Parking is available at the Jennison Building, however, please ensure that you are parked within a bay.

Chips (Programmable Logic, Computer Conservation with FPGAs, OpenCores & OpenRISC 1000)

via OSHUG

Programmable logic, and in particular field-programmable gate arrays (FPGAs), is a topic that has frequently come up at OSHUG meetings, both in informal discussion and in presentations (see use of FPGAs in projects covered at OSHUG #5 & OSHUG #8).

This is a particularly exciting technology in the context of open source hardware, as it presents an opportunity to realise performance gains approaching those that are associated with custom silicon – an Application-Specific Integrated Circuit (ASIC) - albeit without the enormous foundry start-up costs which make this largely the reserve of major industry. Furthermore, the design artefacts lend themselves to collaborative development and can be handled in a manner similar to that employed with the source code to computer software.

At the ninth OSHUG meeting we will be given an introduction to programmable logic and the associated development cycle, we'll hear about applications in computer conservation, and we will learn about open source chip design, the OpenCores community and the MIPS-like OpenRISC 1000 CPU.

A Brief Introduction to Programmable Logic

Programmable Logic Devices - mainly FPGAs – are frequently utilised in high speed and computationally intensive applications, and with modern devices containing several million transistors and many gigabits/second of connectivity they are becoming increasingly popular in the race to achieve exascale computing power.

But what does this all mean and how can FPGAs achieve this processing power? How do they differ from the good old CPUs we have in our everyday computers?

In essence, an FPGA is a device that contains configurable blocks of logic along with flexible interconnect between these blocks. They can be configured to contain exactly and only those operations that appear in the algorithms employed in a particular application, which can potentially give them quite a bit of an advantage in terms of throughput and efficiency when compared to static instruction set processors such as a traditional x86 CPU.

In this short introductory talk we will cover the basics of programmable logic devices and talk about the design, synthesis, simulation, implementation and programming cycles associated with FPGA projects.

Omer Kilic is a research student at the University of Kent working on dynamically reconfigurable architectures and embedded systems. When he is not busy working on his PhD project (a reconfigurable heterogeneous computing framework) or running lab classes, he enjoys tinkering and drinking good beer.

Computer Conservation with FPGAs

Having acquired an IBM System/360 Model 30 mainframe whilst he was at university, Lawrence Wilkinson brought it back to life, then abandoned it when the rent and power costs became a drain, and has since felt very guilty. As they became obsolete in the early 1970s, very few IBM System/360s now exist in running order. To make amends he embarked on a project of re-creating the Model 30 as a gate-level simulation, using the original circuits and microcode. While the software-based Hercules emulator is available to run all 360 and 370 software, Lawrence's programmable logic-based solution faithfully replicates the Model 30 with its limited storage and I/O capability, and provides a front panel interface. The basic CPU is implemented in a Xilinx S3 FPGA and the VHDL is available for download under the GPL. Development of the project continues with the further addition of storage and I/O devices.

Lawrence Wilkinson started out as an Electrical and Electronic Engineer in Auckland in the 1980s, transmogrified into an IT and Accounting support person in the late 80s, then went back to hardware and low-level software upon moving to England in the mid 90s. Eventually ending up with the new BAR Formula 1 team, he spent a few years writing and supporting on-car control software, won the World Championship with Brawn Grand Prix in 2009, and currently supports various factory test systems for Mercedes-Benz Grand Prix in Northamptonshire.

OpenCores, Chip Design and the OpenRISC 1000

Opencores dates back to 1999 as a forum for open source chip designs, primarily intended for FPGA, but also used in ASIC. It now hosts several hundred designs, and has over 100,000 registered users world wide.

This talk will look at what is involved in putting together an open source chip design. In particular the licensing issues represent a challenge, with standard F/OSS licenses having serious weaknesses when it comes to licensing hardware.

It will finish with an overview of OpenCores' flagship project, the OpenRISC 1000. This is a 32-bit MIPS-like RISC processor, with a full reference SoC design. It comes with a GNU development tool chain, a number of RTOS ports and an up to date uClibc Linux kernel/BusyBox implementation. In recent years the entire front-end design flow has become open source, as open source electronic design automation (EDA) tools have become available. It has now reached the stage of maturity where some of its development is by commercially funded engineers, as well as a large community of volunteers.

Dr Jeremy Bennett is Chief Executive of Embecosm Limited. Embecosmi provides open source services, tools and models to facilitate embedded software development with complex systems-on chip. He spends two days a month working as the Embedded Systems Champion for the Electronics, Sensors and Photonics KTN, which seeks to improve the flow of knowledge between academia and industry. He can be contacted via jeremy.bennett@embecosm.com.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt.

Chips (Programmable Logic, Computer Conservation with FPGAs, OpenCores & OpenRISC 1000)

via OSHUG

Programmable logic, and in particular field-programmable gate arrays (FPGAs), is a topic that has frequently come up at OSHUG meetings, both in informal discussion and in presentations (see use of FPGAs in projects covered at OSHUG #5 & OSHUG #8).

This is a particularly exciting technology in the context of open source hardware, as it presents an opportunity to realise performance gains approaching those that are associated with custom silicon – an Application-Specific Integrated Circuit (ASIC) - albeit without the enormous foundry start-up costs which make this largely the reserve of major industry. Furthermore, the design artefacts lend themselves to collaborative development and can be handled in a manner similar to that employed with the source code to computer software.

At the ninth OSHUG meeting we will be given an introduction to programmable logic and the associated development cycle, we'll hear about applications in computer conservation, and we will learn about open source chip design, the OpenCores community and the MIPS-like OpenRISC 1000 CPU.

A Brief Introduction to Programmable Logic

Programmable Logic Devices - mainly FPGAs – are frequently utilised in high speed and computationally intensive applications, and with modern devices containing several million transistors and many gigabits/second of connectivity they are becoming increasingly popular in the race to achieve exascale computing power.

But what does this all mean and how can FPGAs achieve this processing power? How do they differ from the good old CPUs we have in our everyday computers?

In essence, an FPGA is a device that contains configurable blocks of logic along with flexible interconnect between these blocks. They can be configured to contain exactly and only those operations that appear in the algorithms employed in a particular application, which can potentially give them quite a bit of an advantage in terms of throughput and efficiency when compared to static instruction set processors such as a traditional x86 CPU.

In this short introductory talk we will cover the basics of programmable logic devices and talk about the design, synthesis, simulation, implementation and programming cycles associated with FPGA projects.

Omer Kilic is a research student at the University of Kent working on dynamically reconfigurable architectures and embedded systems. When he is not busy working on his PhD project (a reconfigurable heterogeneous computing framework) or running lab classes, he enjoys tinkering and drinking good beer.

Computer Conservation with FPGAs

Having acquired an IBM System/360 Model 30 mainframe whilst he was at university, Lawrence Wilkinson brought it back to life, then abandoned it when the rent and power costs became a drain, and has since felt very guilty. As they became obsolete in the early 1970s, very few IBM System/360s now exist in running order. To make amends he embarked on a project of re-creating the Model 30 as a gate-level simulation, using the original circuits and microcode. While the software-based Hercules emulator is available to run all 360 and 370 software, Lawrence's programmable logic-based solution faithfully replicates the Model 30 with its limited storage and I/O capability, and provides a front panel interface. The basic CPU is implemented in a Xilinx S3 FPGA and the VHDL is available for download under the GPL. Development of the project continues with the further addition of storage and I/O devices.

Lawrence Wilkinson started out as an Electrical and Electronic Engineer in Auckland in the 1980s, transmogrified into an IT and Accounting support person in the late 80s, then went back to hardware and low-level software upon moving to England in the mid 90s. Eventually ending up with the new BAR Formula 1 team, he spent a few years writing and supporting on-car control software, won the World Championship with Brawn Grand Prix in 2009, and currently supports various factory test systems for Mercedes-Benz Grand Prix in Northamptonshire.

OpenCores, Chip Design and the OpenRISC 1000

Opencores dates back to 1999 as a forum for open source chip designs, primarily intended for FPGA, but also used in ASIC. It now hosts several hundred designs, and has over 100,000 registered users world wide.

This talk will look at what is involved in putting together an open source chip design. In particular the licensing issues represent a challenge, with standard F/OSS licenses having serious weaknesses when it comes to licensing hardware.

It will finish with an overview of OpenCores' flagship project, the OpenRISC 1000. This is a 32-bit MIPS-like RISC processor, with a full reference SoC design. It comes with a GNU development tool chain, a number of RTOS ports and an up to date uClibc Linux kernel/BusyBox implementation. In recent years the entire front-end design flow has become open source, as open source electronic design automation (EDA) tools have become available. It has now reached the stage of maturity where some of its development is by commercially funded engineers, as well as a large community of volunteers.

Dr Jeremy Bennett is Chief Executive of Embecosm Limited. Embecosmi provides open source services, tools and models to facilitate embedded software development with complex systems-on chip. He spends two days a month working as the Embedded Systems Champion for the Electronics, Sensors and Photonics KTN, which seeks to improve the flow of knowledge between academia and industry. He can be contacted via jeremy.bennett@embecosm.com.

Note: Please aim to arrive for 18:00 - 18:20 as the event will start at 18:30 prompt.

Performance (MilkyMist)

via OSHUG

It stands to reason that hardware which is open to being studied, modified and improved would be well suited to performance environments, and just as F/OSS has proved popular in support of creative practices so is OSHW similarly gaining favour. With designs ranging from simple electronic instruments that make for an ideal first electronics project to vastly more complex processing and synthesis devices.

At the eighth OSHUG meeting we'll be hearing about the Milkymist™ project which "develops a comprehensive open source solution for the live synthesis of interactive visual effects for VJs (video performance artists)".

MilkyMist - An FPGA-based open-hardware video synthesis platform

The MilkyMist project develops a stand-alone device in a small form factor that is capable of rendering MilkDrop-esque visuals effects in real time, with a high level of interaction with many sensors and using live audio and video streams as a base. The flexibility of the FPGA used as a central component enables advanced users to modify the design, and also permits compact integration of many interfaces (Ethernet, OSC, MIDI, DMX512, video inputs, GPIO, VGA output, USB, Irda ...), making Milkymist™ a platform of choice for the mobile VJ. But Milkymist™ is more than a visual synthesizer - it is also one of the leading open source system-on-chip designs. It is today the fastest open source system-on-chip capable of running Linux, and it comes with an extensive set of features and graphics accelerators. The IP cores that make up the system-on-chip are entirely written in open source synthesizable Verilog HDL and come with test benches and documentation, which makes Milkymist™ a great library of re-usable logic cores to serve as a base for other open source hardware.

Yann Sionneau is a twenty two year old Frenchman and soon to be graduated from the telecommunication and networking engineering school Télécom SudParis. His current interests in the main are low level software development, FPGA design, embedded systems and networks. He read his first C language book when he was 12 and fell in love with the language. He met Sebastien Bourdeauducq (aka lekernel), leader of the Milkymist project, in 2008 while doing whilst an intern at a startup co-founded by Sebastien. He ported RTEMS to Milkymist as part of the Google Summer of Code 2010 program and has been following the project for some time.

Note: Please aim to arrive for 18:00 - 18:15 as the event will start at 18:30 prompt.

Performance (MilkyMist)

via OSHUG

It stands to reason that hardware which is open to being studied, modified and improved would be well suited to performance environments, and just as F/OSS has proved popular in support of creative practices so is OSHW similarly gaining favour. With designs ranging from simple electronic instruments that make for an ideal first electronics project to vastly more complex processing and synthesis devices.

At the eighth OSHUG meeting we'll be hearing about the Milkymist™ project which "develops a comprehensive open source solution for the live synthesis of interactive visual effects for VJs (video performance artists)".

MilkyMist - An FPGA-based open-hardware video synthesis platform

The MilkyMist project develops a stand-alone device in a small form factor that is capable of rendering MilkDrop-esque visuals effects in real time, with a high level of interaction with many sensors and using live audio and video streams as a base. The flexibility of the FPGA used as a central component enables advanced users to modify the design, and also permits compact integration of many interfaces (Ethernet, OSC, MIDI, DMX512, video inputs, GPIO, VGA output, USB, Irda ...), making Milkymist™ a platform of choice for the mobile VJ. But Milkymist™ is more than a visual synthesizer - it is also one of the leading open source system-on-chip designs. It is today the fastest open source system-on-chip capable of running Linux, and it comes with an extensive set of features and graphics accelerators. The IP cores that make up the system-on-chip are entirely written in open source synthesizable Verilog HDL and come with test benches and documentation, which makes Milkymist™ a great library of re-usable logic cores to serve as a base for other open source hardware.

Yann Sionneau is a twenty two year old Frenchman and soon to be graduated from the telecommunication and networking engineering school Télécom SudParis. His current interests in the main are low level software development, FPGA design, embedded systems and networks. He read his first C language book when he was 12 and fell in love with the language. He met Sebastien Bourdeauducq (aka lekernel), leader of the Milkymist project, in 2008 while doing whilst an intern at a startup co-founded by Sebastien. He ported RTEMS to Milkymist as part of the Google Summer of Code 2010 program and has been following the project for some time.

Note: Please aim to arrive for 18:00 - 18:15 as the event will start at 18:30 prompt.